diff mbox series

[U-Boot,v2,20/29] riscv: remove unused labels in start.S

Message ID	20181030125553.5230-21-lukas.auer@aisec.fraunhofer.de
State	Superseded
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> To: <u-boot@lists.denx.de> Date: Tue, 30 Oct 2018 13:55:43 +0100 Message-ID: <20181030125553.5230-21-lukas.auer@aisec.fraunhofer.de> In-Reply-To: <20181030125553.5230-1-lukas.auer@aisec.fraunhofer.de> References: <20181030125553.5230-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 Cc: Greentime Hu <green.hu@gmail.com> Subject: [U-Boot] [PATCH v2 20/29] riscv: remove unused labels in start.S Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	General fixes / cleanup for RISC-V and improvements to qemu-riscv \| expand [U-Boot,v2,00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv [U-Boot,v2,01/29] tools: .gitignore: add prelink-riscv [U-Boot,v2,02/29] dts: riscv: update makefile to also clean the RISC-V dts directory [U-Boot,v2,03/29] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I [U-Boot,v2,04/29] riscv: select CONFIG_PHYS_64BIT on RV64I systems [U-Boot,v2,05/29] riscv: add Kconfig entries for the C and A ISA extensions [U-Boot,v2,06/29] riscv: set -march and -mabi based on the Kconfig configuration [U-Boot,v2,07/29] riscv: add Kconfig entries for the code model [U-Boot,v2,08/29] riscv: enable -fdata-sections [U-Boot,v2,09/29] riscv: fix use of incorrectly sized variables [U-Boot,v2,10/29] riscv: make use of the barrier functions from Linux [U-Boot,v2,11/29] riscv: do not reimplement generic io functions [U-Boot,v2,12/29] riscv: complete the list of exception codes [U-Boot,v2,13/29] riscv: treat undefined exception codes as reserved [U-Boot,v2,14/29] riscv: hang on unhandled exceptions [U-Boot,v2,15/29] riscv: implement the invalidate_icache_* functions [U-Boot,v2,16/29] riscv: invalidate the instruction cache before jumping to Linux [U-Boot,v2,17/29] riscv: fix inconsistent use of spaces and tabs in start.S [U-Boot,v2,18/29] riscv: align mtvec on a 4-byte boundary [U-Boot,v2,19/29] Drop CONFIG_INIT_CRITICAL [U-Boot,v2,20/29] riscv: remove unused labels in start.S [U-Boot,v2,21/29] riscv: do not blindly modify the mstatus CSR [U-Boot,v2,22/29] riscv: save hart ID and device tree passed by prior boot stage [U-Boot,v2,23/29] riscv: qemu: use device tree passed by prior boot stage [U-Boot,v2,24/29] riscv: store device tree passed by prior boot stage in environment [U-Boot,v2,25/29] riscv: qemu: support booting Linux [U-Boot,v2,26/29] riscv: align bootm implementation with that of other architectures [U-Boot,v2,27/29] dm: core: add missing prototype for ofnode_read_u64 [U-Boot,v2,28/29] riscv: qemu: detect and boot the kernel passed by QEMU [U-Boot,v2,29/29] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL

Commit Message

Lukas Auer Oct. 30, 2018, 12:55 p.m. UTC

The labels nmi_vector, trap_vector and handle_reset in start.S are not
used for RISC-V. Remove them.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---

Changes in v2:
- Drop removal of code that stores the contents of a2; this broke the
board ax25-ae350. The code will be removed again in a future patch.

 arch/riscv/cpu/start.S | 9 ---------
 1 file changed, 9 deletions(-)

Comments

Bin Meng Oct. 31, 2018, 2:14 a.m. UTC | #1

On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> The labels nmi_vector, trap_vector and handle_reset in start.S are not
> used for RISC-V. Remove them.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Drop removal of code that stores the contents of a2; this broke the
> board ax25-ae350. The code will be removed again in a future patch.
>
>  arch/riscv/cpu/start.S | 9 ---------
>  1 file changed, 9 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff mbox series

Patch

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 9804a8ac44..c313477ae0 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -34,15 +34,6 @@ 
 .section .text
 .globl _start
 _start:
-	j	handle_reset
-
-nmi_vector:
-	j	nmi_vector
-
-trap_vector:
-	j	trap_entry
-
-handle_reset:
 	li	t0, CONFIG_SYS_SDRAM_BASE
 	SREG	a2, 0(t0)
 	la	t0, trap_entry