| Message ID | 20181025092307.28201-5-icenowy@aosc.io |
|---|---|
| State | Accepted |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | sunxi: extend SPL header to propagate DRAM size and H6 3GiB DRAM support | expand |
On 10/25/18 10:23 AM, Icenowy Zheng wrote: > All Allwinner 64-bit SoCs now are known to be able to access 3GiB of > external DRAM, however the size of DRAM part in the MMU translation > table is still 2GiB. > > Change the size of DRAM part in MMU table to 3GiB. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre. > --- > This used to be in another patchset targeting 3GiB support. > > No changes in v2. > > arch/arm/mach-sunxi/board.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c > index d22a84ea6b..b74eaf2a0e 100644 > --- a/arch/arm/mach-sunxi/board.c > +++ b/arch/arm/mach-sunxi/board.c > @@ -52,7 +52,7 @@ static struct mm_region sunxi_mem_map[] = { > /* RAM */ > .virt = 0x40000000UL, > .phys = 0x40000000UL, > - .size = 0x80000000UL, > + .size = 0xC0000000UL, > .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | > PTE_BLOCK_INNER_SHARE > }, { >
On Thu, Oct 25, 2018 at 2:53 PM Icenowy Zheng <icenowy@aosc.io> wrote: > > All Allwinner 64-bit SoCs now are known to be able to access 3GiB of > external DRAM, however the size of DRAM part in the MMU translation > table is still 2GiB. > > Change the size of DRAM part in MMU table to 3GiB. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- Reviewed-by: Jagan Teki <jagan@openedev.com> Applied to u-boot-sunxi/master
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index d22a84ea6b..b74eaf2a0e 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -52,7 +52,7 @@ static struct mm_region sunxi_mem_map[] = { /* RAM */ .virt = 0x40000000UL, .phys = 0x40000000UL, - .size = 0x80000000UL, + .size = 0xC0000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, {
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of external DRAM, however the size of DRAM part in the MMU translation table is still 2GiB. Change the size of DRAM part in MMU table to 3GiB. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- This used to be in another patchset targeting 3GiB support. No changes in v2. arch/arm/mach-sunxi/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)