From patchwork Fri Oct 19 22:07:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 987060 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42cKrN0tkZz9sjG for ; Sat, 20 Oct 2018 09:11:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BFF1CC21C93; Fri, 19 Oct 2018 22:09:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BCD31C21CB1; Fri, 19 Oct 2018 22:09:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1B138C21CB6; Fri, 19 Oct 2018 22:09:12 +0000 (UTC) Received: from mail-edgeS23.fraunhofer.de (mail-edges23.fraunhofer.de [153.97.7.23]) by lists.denx.de (Postfix) with ESMTPS id ACF55C21D8A for ; Fri, 19 Oct 2018 22:09:08 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2EKAABKVcpb/xwBYJlkGgEBAQEBAgEBAQEHAgEBAQGBUgQBAQEBCwGCBIFTOoxsizuDB5YVgXoNhGwChQkhNQwNAQMBAQIBAQICAmkohTwGeRAdND0MDgYOBYMhggEBqH+KGgkBhyKEI4FYP4EQAYJdiw0CnkEHAoENgQEEjk8LF4krhn4sliaBRQE2gVUzGiSDO4JPjgptAYwkAQE X-IPAS-Result: A2EKAABKVcpb/xwBYJlkGgEBAQEBAgEBAQEHAgEBAQGBUgQBAQEBCwGCBIFTOoxsizuDB5YVgXoNhGwChQkhNQwNAQMBAQIBAQICAmkohTwGeRAdND0MDgYOBYMhggEBqH+KGgkBhyKEI4FYP4EQAYJdiw0CnkEHAoENgQEEjk8LF4krhn4sliaBRQE2gVUzGiSDO4JPjgptAYwkAQE X-IronPort-AV: E=Sophos;i="5.54,401,1534802400"; d="scan'208";a="6664182" Received: from mail-mtaka28.fraunhofer.de ([153.96.1.28]) by mail-edgeS23.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Oct 2018 00:09:08 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0A3AAAiVcpb/xBhWMBkHAEBAQQBAQcEAQGBUgYBAQsBhBGMbI5ClhWBeg2EbAKFKTUMDQEDAQECAQECbSiFOwZ5EB00PQwOBg4FgyGCAqh/ihoJAYcihXs/gRABgl2LDQKeQQcCgQ2BAQSOTwsXiSuGfiyWJoFFATWBVTMaJIM7gk+OCj0wAYwkAQE X-IronPort-AV: E=Sophos;i="5.54,401,1534802400"; d="scan'208";a="18910093" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP11EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA28.fraunhofer.de with ESMTP/TLS/AES256-SHA; 20 Oct 2018 00:09:08 +0200 Received: from localhost.de (10.80.233.50) by FGDEMUCIMP11EXC.ads.fraunhofer.de (10.80.232.42) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sat, 20 Oct 2018 00:10:26 +0200 From: Lukas Auer To: Date: Sat, 20 Oct 2018 00:07:17 +0200 Message-ID: <20181019220743.15020-5-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181019220743.15020-1-lukas.auer@aisec.fraunhofer.de> References: <20181019220743.15020-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24166.002 X-TM-AS-Result: No--3.348900-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Heinrich Schuchardt , Alexander Graf Subject: [U-Boot] [PATCH 04/30] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_64I to match this convention. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 16 ++++++++-------- arch/riscv/lib/setjmp.S | 2 +- configs/ax25-ae350_defconfig | 2 +- configs/qemu-riscv64_defconfig | 2 +- include/config_distro_bootcmd.h | 8 ++++---- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 168ca3de7c..7c76b4d664 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -20,20 +20,20 @@ source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" choice - prompt "CPU selection" - default CPU_RISCV_32 + prompt "Base ISA" + default ARCH_RV32I -config CPU_RISCV_32 - bool "RISC-V 32-bit" +config ARCH_RV32I + bool "RV32I" select 32BIT help - Choose this option to build an U-Boot for RISCV32 architecture. + Choose this option to target the RV32I base integer instruction set. -config CPU_RISCV_64 - bool "RISC-V 64-bit" +config ARCH_RV64I + bool "RV64I" select 64BIT help - Choose this option to build an U-Boot for RISCV64 architecture. + Choose this option to target the RV64I base integer instruction set. endchoice diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S index 8f5a6a23aa..72bc9241f6 100644 --- a/arch/riscv/lib/setjmp.S +++ b/arch/riscv/lib/setjmp.S @@ -6,7 +6,7 @@ #include #include -#ifdef CONFIG_CPU_RISCV_64 +#ifdef CONFIG_ARCH_RV64I #define STORE_IDX(reg, idx) sd reg, (idx*8)(a0) #define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0) #else diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig index 614ef15dc7..9282f05981 100644 --- a/configs/ax25-ae350_defconfig +++ b/configs/ax25-ae350_defconfig @@ -1,7 +1,7 @@ CONFIG_RISCV=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_AX25_AE350=y -CONFIG_CPU_RISCV_64=y +CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_FIT=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index d6c1a5d646..60b647efe8 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -1,6 +1,6 @@ CONFIG_RISCV=y CONFIG_TARGET_QEMU_VIRT=y -CONFIG_CPU_RISCV_64=y +CONFIG_ARCH_RV64I=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 373fee78a9..54186efe7b 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -99,9 +99,9 @@ #define BOOTEFI_NAME "bootia32.efi" #elif defined(CONFIG_X86_RUN_64BIT) #define BOOTEFI_NAME "bootx64.efi" -#elif defined(CONFIG_CPU_RISCV_32) +#elif defined(CONFIG_ARCH_RV32I) #define BOOTEFI_NAME "bootriscv32.efi" -#elif defined(CONFIG_CPU_RISCV_64) +#elif defined(CONFIG_ARCH_RV64I) #define BOOTEFI_NAME "bootriscv64.efi" #endif #endif @@ -257,10 +257,10 @@ #elif defined(__i386__) #define BOOTENV_EFI_PXE_ARCH "0x6" #define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00006:UNDI:003000" -#elif defined(CONFIG_CPU_RISCV_32) || ((defined(__riscv) && __riscv_xlen == 32)) +#elif defined(CONFIG_ARCH_RV32I) || ((defined(__riscv) && __riscv_xlen == 32)) #define BOOTENV_EFI_PXE_ARCH "0x19" #define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00025:UNDI:003000" -#elif defined(CONFIG_CPU_RISCV_64) || ((defined(__riscv) && __riscv_xlen == 64)) +#elif defined(CONFIG_ARCH_RV64I) || ((defined(__riscv) && __riscv_xlen == 64)) #define BOOTENV_EFI_PXE_ARCH "0x1b" #define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00027:UNDI:003000" #elif defined(CONFIG_SANDBOX)