From patchwork Fri Oct 19 22:07:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 987088 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42cLCj5d24z9sj7 for ; Sat, 20 Oct 2018 09:28:17 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6F477C21DD7; Fri, 19 Oct 2018 22:17:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7C7EEC21E34; Fri, 19 Oct 2018 22:15:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BC10DC21DE8; Fri, 19 Oct 2018 22:11:14 +0000 (UTC) Received: from mail-edgeDD24.fraunhofer.de (mail-edgeDD24.fraunhofer.de [192.102.167.24]) by lists.denx.de (Postfix) with ESMTPS id 79E8AC21D72 for ; Fri, 19 Oct 2018 22:11:13 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2EKAACcVcpb/xwBYJlkGgEBAQEBAgEBAQEHAgEBAQGBUgQBAQEBCwGBWiqBUzqMbIs7mRyBeg2EbAKFCSE1DA0BAwEBAgEBAgICaSiFPAZ5EFE9GgYOBYMhggEBqH+KGgkBhyKEI4FYP4EQAYhdhQ0CiHqVRwcCgQ2BAQSOTwsXiSuGfpZSgUUDNIFVMxokgzuDOgEBjR1tAYwkAQE X-IPAS-Result: A2EKAACcVcpb/xwBYJlkGgEBAQEBAgEBAQEHAgEBAQGBUgQBAQEBCwGBWiqBUzqMbIs7mRyBeg2EbAKFCSE1DA0BAwEBAgEBAgICaSiFPAZ5EFE9GgYOBYMhggEBqH+KGgkBhyKEI4FYP4EQAYhdhQ0CiHqVRwcCgQ2BAQSOTwsXiSuGfpZSgUUDNIFVMxokgzuDOgEBjR1tAYwkAQE X-IronPort-AV: E=Sophos;i="5.54,401,1534802400"; d="scan'208";a="7272594" Received: from mail-mtaka28.fraunhofer.de ([153.96.1.28]) by mail-edgeDD24.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Oct 2018 00:11:13 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0A3AAAHVspb/xBhWMBkHAEBAQQBAQcEAQGBUgYBAQsBgVqCN4xspFeBeg2EbAKFKTUMDQEDAQECAQECbSiFOwZ5EFE9GgYOBYMhggKoe4obCQGHIoV7P4EQAYhdhQ0CiHqVRwcCgQ2BAQSOTwsXiSuGfpZSgUUDM4FVMxokgzuDOgEBjR09MAGMJAEB X-IronPort-AV: E=Sophos;i="5.54,401,1534802400"; d="scan'208";a="18910115" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP11EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA28.fraunhofer.de with ESMTP/TLS/AES256-SHA; 20 Oct 2018 00:10:53 +0200 Received: from localhost.de (10.80.233.50) by FGDEMUCIMP11EXC.ads.fraunhofer.de (10.80.232.42) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sat, 20 Oct 2018 00:12:11 +0200 From: Lukas Auer To: Date: Sat, 20 Oct 2018 00:07:36 +0200 Message-ID: <20181019220743.15020-24-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181019220743.15020-1-lukas.auer@aisec.fraunhofer.de> References: <20181019220743.15020-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24166.002 X-TM-AS-Result: No--3.656000-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Greentime Hu Subject: [U-Boot] [PATCH 23/30] riscv: do not blindly modify the mstatus CSR X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The mstatus CSR includes WPRI (writes preserve values, reads ignore values) fields and must therefore not be set to zero without preserving these fields. It is not apparent why mstatus is set to zero here since it is not required for u-boot to run. Remove it. This instruction and others encode zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/cpu/start.S | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 851a1d0870..4fa663c6d6 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -36,9 +36,9 @@ _start: la t0, trap_entry csrw mtvec, t0 - csrwi mstatus, 0 - csrwi mie, 0 + /* mask all interrupts */ + csrw mie, zero /* * Set stackpointer in internal/ex RAM to call board_init_f @@ -159,11 +159,10 @@ clear_bss: add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ - li t2, 0x00000000 /* clear */ beq t0, t1, call_board_init_r clbss_l: - SREG t2, 0(t0) /* clear loop... */ + SREG zero, 0(t0) /* clear loop... */ addi t0, t0, REGBYTES bne t0, t1, clbss_l