| Message ID | 20181019220743.15020-24-lukas.auer@aisec.fraunhofer.de |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | General fixes / cleanup for RISC-V and improvements to qemu-riscv | expand |
On Sat, Oct 20, 2018 at 6:11 AM Lukas Auer <lukas.auer@aisec.fraunhofer.de> wrote: > > The mstatus CSR includes WPRI (writes preserve values, reads ignore > values) fields and must therefore not be set to zero without preserving > these fields. It is not apparent why mstatus is set to zero here since > it is not required for u-boot to run. Remove it. nits: U-Boot > > This instruction and others encode zero as an immediate. RISC-V has the > zero register for this purpose. Replace the immediates with the zero > register. > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > --- > > arch/riscv/cpu/start.S | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > > > > > The mstatus CSR includes WPRI (writes preserve values, reads ignore > > > values) fields and must therefore not be set to zero without > > > preserving these fields. It is not apparent why mstatus is set to zero > > > here since it is not required for u-boot to run. Remove it. > > > > nits: U-Boot > > > > > > > > This instruction and others encode zero as an immediate. RISC-V has > > > the zero register for this purpose. Replace the immediates with the > > > zero register. > > > > > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > > > --- > > > > > > arch/riscv/cpu/start.S | 7 +++---- > > > 1 file changed, 3 insertions(+), 4 deletions(-) > > > > > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 851a1d0870..4fa663c6d6 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -36,9 +36,9 @@ _start: la t0, trap_entry csrw mtvec, t0 - csrwi mstatus, 0 - csrwi mie, 0 + /* mask all interrupts */ + csrw mie, zero /* * Set stackpointer in internal/ex RAM to call board_init_f @@ -159,11 +159,10 @@ clear_bss: add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ - li t2, 0x00000000 /* clear */ beq t0, t1, call_board_init_r clbss_l: - SREG t2, 0(t0) /* clear loop... */ + SREG zero, 0(t0) /* clear loop... */ addi t0, t0, REGBYTES bne t0, t1, clbss_l
The mstatus CSR includes WPRI (writes preserve values, reads ignore values) fields and must therefore not be set to zero without preserving these fields. It is not apparent why mstatus is set to zero here since it is not required for u-boot to run. Remove it. This instruction and others encode zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> --- arch/riscv/cpu/start.S | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)