From patchwork Fri Oct 19 22:07:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 987071 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42cL1P0GzPz9t0P for ; Sat, 20 Oct 2018 09:19:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B6C52C21DB3; Fri, 19 Oct 2018 22:12:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B518EC21E0D; Fri, 19 Oct 2018 22:12:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E3448C21DFD; Fri, 19 Oct 2018 22:10:42 +0000 (UTC) Received: from mail-edgeS23.fraunhofer.de (mail-edges23.fraunhofer.de [153.97.7.23]) by lists.denx.de (Postfix) with ESMTPS id AB626C21E02 for ; Fri, 19 Oct 2018 22:10:38 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2GMAABKVcpb/xwBYJlkGgEBAQEBAgEBAQEHAgEBAQGBZYIFgVM6jGyLO5QwhmYNgUeDJQKFCSE4FgEDAQECAQECAgJpKIU8BnkQUT0aBg4FgyGCAQGof4oaCQGHIoQjgVg/gRABiF2FDQKeQQcCgQ2BAQSOTwsXiSuGfiyWJoFaIoFVMxokgzuCJheOHG0BjCQBAQ X-IPAS-Result: A2GMAABKVcpb/xwBYJlkGgEBAQEBAgEBAQEHAgEBAQGBZYIFgVM6jGyLO5QwhmYNgUeDJQKFCSE4FgEDAQECAQECAgJpKIU8BnkQUT0aBg4FgyGCAQGof4oaCQGHIoQjgVg/gRABiF2FDQKeQQcCgQ2BAQSOTwsXiSuGfiyWJoFaIoFVMxokgzuCJheOHG0BjCQBAQ X-IronPort-AV: E=Sophos;i="5.54,401,1534802400"; d="scan'208";a="6664209" Received: from mail-mtaka28.fraunhofer.de ([153.96.1.28]) by mail-edgeS23.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Oct 2018 00:10:38 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0D+AgAiVcpb/xBhWMBkHAEBAQQBAQcEAQGBZYQSjGyfa4ZmDYFHgyUChSk4FgEDAQECAQECbSiFOwZ5EFE9GgYOBYMhggKof4oaCQGHIoV7P4EQAYhdhQ0CnkEHAoENgQEEjk8LF4krhn4sliaBWiGBVTMaJIM7giYXjhw9MAGMJAEB X-IronPort-AV: E=Sophos;i="5.54,401,1534802400"; d="scan'208";a="18910108" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP11EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA28.fraunhofer.de with ESMTP/TLS/AES256-SHA; 20 Oct 2018 00:10:38 +0200 Received: from localhost.de (10.80.233.50) by FGDEMUCIMP11EXC.ads.fraunhofer.de (10.80.232.42) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sat, 20 Oct 2018 00:11:57 +0200 From: Lukas Auer To: Date: Sat, 20 Oct 2018 00:07:30 +0200 Message-ID: <20181019220743.15020-18-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181019220743.15020-1-lukas.auer@aisec.fraunhofer.de> References: <20181019220743.15020-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24166.002 X-TM-AS-Result: No-0.614700-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Greentime Hu Subject: [U-Boot] [PATCH 17/30] riscv: implement the invalidate_icache_* functions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/lib/cache.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 1d67c49c2c..d642a38a07 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -12,6 +12,16 @@ void flush_dcache_range(unsigned long start, unsigned long end) void invalidate_icache_range(unsigned long start, unsigned long end) { + /* + * RISC-V does not have an instruction for invalidating parts of the + * instruction cache. Invalidate all of it instead. + */ + invalidate_icache_all(); +} + +void invalidate_icache_all(void) +{ + asm volatile ("fence.i" ::: "memory"); } void invalidate_dcache_range(unsigned long start, unsigned long end)