From patchwork Fri Sep 7 08:24:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 967277 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ENnEhd8v"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4269TW1ypvz9s3x for ; Fri, 7 Sep 2018 18:24:29 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1F09DC21E30; Fri, 7 Sep 2018 08:24:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 31D33C21D4A; Fri, 7 Sep 2018 08:24:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1488EC21D4A; Fri, 7 Sep 2018 08:24:16 +0000 (UTC) Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) by lists.denx.de (Postfix) with ESMTPS id 6A183C21BE5 for ; Fri, 7 Sep 2018 08:24:15 +0000 (UTC) Received: by mail-pg1-f195.google.com with SMTP id v66-v6so6615761pgb.10 for ; Fri, 07 Sep 2018 01:24:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=uCjLF1WYFrYcxZjdvZPWOuWcqyWVV066OcMVf2ee9hQ=; b=ENnEhd8vXmY4i+7ZS4Gb/lSFKXWBDMNLzbJb4KEKDT4GHQ2kX/TT4WwSVof8tF2IDj 0CbTe1uirlTc9Wom0gCioRTSMpicOxdIj+5b+OzI26gC/l2JVnaXk3f5O3H0v2yZDr7H iJALeZNTeiXkPVFKYpU1qLFwsZPoyBuGxJfL6LlH4Fogfc/JWKNL8CIBYnFLkrYCuZvw GMIHr9eb5cpg88GGg6qd66p/P55kIBJY3SR8Tgi2/tjZR7FjVD5TxFaX1xWF673WiNTr typ/GMQQ+g5+qNiz2N/AKsIIEJw7KrKnyRQUYdRVrwlfbVdfkb7/vi42sspSecQ+DaXu k9vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=uCjLF1WYFrYcxZjdvZPWOuWcqyWVV066OcMVf2ee9hQ=; b=HrK6aXbjGIJLoH8XY4FvVc9VsIGb7hfRiX9SdFqF61izkIGKR/QGL0Hmu59Fm6X4j5 w0/56jDP6hNe4sI021CiSKhBvvbNVt8zrxqq/mQbA9K92P5oqKbFcwJHVLKiYBDdJVmu /9zfFV/ut3viCN2kOiyCxEGlxLl3WpvYgDFhOThnv2aMN3RlBc6+pcatgcYAr3Av57e8 BrAYc5Qk+WCzMi1xzHvBELmPqYsHGgJG79764pJhewMecsxg/4nA/SaA6U4sIFBakia6 l7p6G2y/rLPxO6g79QIAfCsauNbadAqv+pDu7BsTr+0f8fALEGzJHX0r3ucXGqQwkMsk a9Ow== X-Gm-Message-State: APzg51Db74AOHIDxX+qg21cimleQE7+eAVZtp/DMsqG8QmWG1PNhLvlg Lg8vPzbXpv3aab5cmIrQxdYVeDpdhvs= X-Google-Smtp-Source: ANB0VdaYdmIA57BGnSr2N+ffD6kA2FBicNPCZk5QhGouHMxNfR9G7PMVsea+rq47cC1oft62kipTJg== X-Received: by 2002:a62:46c8:: with SMTP id o69-v6mr7303507pfi.21.1536308652574; Fri, 07 Sep 2018 01:24:12 -0700 (PDT) Received: from chrisp-dl.ws.atlnz.lc ([2001:df5:b000:22:3a2c:4aff:fe70:2b02]) by smtp.gmail.com with ESMTPSA id 87-v6sm13457731pfn.103.2018.09.07.01.24.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Sep 2018 01:24:11 -0700 (PDT) From: Chris Packham To: u-boot@lists.denx.de Date: Fri, 7 Sep 2018 20:24:04 +1200 Message-Id: <20180907082404.31983-1-judge.packham@gmail.com> X-Mailer: git-send-email 2.18.0 Cc: Paul Davey , Chris Packham Subject: [U-Boot] [RFC PATCH v1] mips: add atomic operations X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add mips version of atomic.h and basic atomic operations. These aren't the optimised versions from the Linux kernel, just basic stubs that satisfy users that need something to define atomic_inc() etc. Signed-off-by: Chris Packham --- At $dayjob we have a mips target that we want to run UBIFS on. UBIFS requires atomic.h. This is my naive attempt to supply enough of atomic.h to satisfy UBIFS. It's no coincidence that this looks like the arm version. I am wondering if it's worth a asm-generic version leaving architectures that actually need true atomic operations able to define them. arch/mips/include/asm/atomic.h | 151 +++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 arch/mips/include/asm/atomic.h diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h new file mode 100644 index 000000000000..3ab5684fdef4 --- /dev/null +++ b/arch/mips/include/asm/atomic.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _ASM_ATOMIC_H +#define _ASM_ATOMIC_H + +#include + +typedef struct { volatile int counter; } atomic_t; +#if BITS_PER_LONG == 32 +typedef struct { volatile long long counter; } atomic64_t; +#else /* BIT_PER_LONG == 32 */ +typedef struct { volatile long counter; } atomic64_t; +#endif + +#define ATOMIC_INIT(i) { (i) } + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v, i) (((v)->counter) = (i)) +#define atomic64_read(v) atomic_read(v) +#define atomic64_set(v, i) atomic_set(v, i) + +static inline void atomic_add(int i, volatile atomic_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, volatile atomic_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +static inline void atomic_inc(volatile atomic_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += 1; + local_irq_restore(flags); +} + +static inline void atomic_dec(volatile atomic_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= 1; + local_irq_restore(flags); +} + +static inline int atomic_dec_and_test(volatile atomic_t *v) +{ + unsigned long flags = 0; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val -= 1; + local_irq_restore(flags); + + return val == 0; +} + +static inline int atomic_add_negative(int i, volatile atomic_t *v) +{ + unsigned long flags = 0; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val += i; + local_irq_restore(flags); + + return val < 0; +} + +static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) +{ + unsigned long flags = 0; + + local_irq_save(flags); + *addr &= ~mask; + local_irq_restore(flags); +} + +#if BITS_PER_LONG == 32 + +static inline void atomic64_add(long long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic64_sub(long long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +#else /* BIT_PER_LONG == 32 */ + +static inline void atomic64_add(long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic64_sub(long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} +#endif /* BIT_PER_LONG == 32 */ + +static inline void atomic64_inc(volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += 1; + local_irq_restore(flags); +} + +static inline void atomic64_dec(volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= 1; + local_irq_restore(flags); +} + +#endif