From patchwork Sun Aug 26 23:13:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniu Rosca X-Patchwork-Id: 962297 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tOGWkaCH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41z9rb1d61z9ryt for ; Mon, 27 Aug 2018 09:16:47 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D17ABC21DD3; Sun, 26 Aug 2018 23:16:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0645FC21E89; Sun, 26 Aug 2018 23:16:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A5B5AC21E5B; Sun, 26 Aug 2018 23:16:05 +0000 (UTC) Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by lists.denx.de (Postfix) with ESMTPS id 045F8C21DE8 for ; Sun, 26 Aug 2018 23:16:02 +0000 (UTC) Received: by mail-wm0-f68.google.com with SMTP id n11-v6so6592134wmc.2 for ; Sun, 26 Aug 2018 16:16:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kV9mVcio8+PgSAAyDi8TnCXYdH0NuP6qT9iLW20Da8k=; b=tOGWkaCHwUN1PQFh8YtK9H0tyDdkiGstZ4Q32YkFGKp11+LegBQrbCEBT+fsgv2OqT LUNl/fDIZqOfi0giPB2P8rEoVG7NqnazXz0qpb5YpYI1yOjNv4v4x3LWTUsyx/fBdVCu 4yYGjIhSgSgP/Zvk/M058ToRvttoZM+XvhWgc1UcIdpO0/uX6lj5PdI1IRbLq3/y1zQY 8WOT0noUaXmhN9w94DcmdCp5+GelFzVne3HYnowFzE4fpjhwQ5ww4ERW5OaThybv2r5O 4MU2Obyq+OPDNpZ3+a3lac59vVBEMqgn4KuIFlvtikycFGJZsplP9z/rnju2XZU8cpxO 27ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kV9mVcio8+PgSAAyDi8TnCXYdH0NuP6qT9iLW20Da8k=; b=fVlKuZ7HLZ/x6lCoqIRH74ZOrLbwhjyZdYZVHEv1AiEOQ2QVUiXtH2liJ5ipbfZv9s QEnIJesSbk5xYkbD2PiaQXqIjd72I2VeJyKXMUAmND/BCtjN9Fxw0HeNzaKlLnw4F3bk /SSitwnk+UgEn31lM8VkwSrm2Go1DTKBoM35RN2s82p/u9sPmg3lDVPfh2ARotOMTF1u /tdqhZqf9r3GxKpfNidmFTSt/CYEcZTwRBujrixYgN0G93T7TiyKORFvmACeOtKF98fN ssCGV3U26iaeUVZh64aLH4dxmCM+E1LQRImr9GZ2S1XTkUaEDXyAUgwV/P8AABhp6KjM CioQ== X-Gm-Message-State: APzg51D/U9smGMWrVVfMbRuj0NykrGoGROJesraXQyJXu9vzAhr8gECg TxDOhxqRpf1/6rUYy4MMkuU= X-Google-Smtp-Source: ANB0Vda/YUZ9VWfFpNxYMfe305EEZchREzKWxx0nnklOSgRJqDkue5ptL/Ql0jvIAh7Vi+9GD3gxUQ== X-Received: by 2002:a1c:ee97:: with SMTP id j23-v6mr4212546wmi.66.1535325361670; Sun, 26 Aug 2018 16:16:01 -0700 (PDT) Received: from localhost.localdomain (ipb218f467.dynamic.kabel-deutschland.de. [178.24.244.103]) by smtp.gmail.com with ESMTPSA id e141-v6sm10828362wmd.32.2018.08.26.16.15.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 26 Aug 2018 16:16:00 -0700 (PDT) From: Eugeniu Rosca X-Google-Original-From: Eugeniu Rosca To: Tom Rini , u-boot@lists.denx.de Date: Mon, 27 Aug 2018 01:13:22 +0200 Message-Id: <20180826231332.2491-5-erosca@de.adit-jv.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180826231332.2491-1-erosca@de.adit-jv.com> References: <20180826231332.2491-1-erosca@de.adit-jv.com> Cc: Takeshi Kihara , Eugeniu Rosca , Eugeniu Rosca , Marek Vasut Subject: [U-Boot] [PATCH v2 04/13] pinctrl: renesas: Fix signed shift overflow X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Booting R-Car H3-Salvator-X (CONFIG_UBSAN=y) consistently results in: ===================================================================== UBSAN: Undefined behaviour in drivers/pinctrl/renesas/pfc.c:402:40 left shift of 1 by 31 places cannot be represented in type 'int' ===================================================================== ===================================================================== UBSAN: Undefined behaviour in drivers/pinctrl/renesas/pfc.c:410:39 left shift of 1 by 31 places cannot be represented in type 'int' ===================================================================== While fixing these warnings, convert *all* SH_PFC_PIN_CFG_* definitions to use the recommended BIT() macro. Fixes: 910df4d07e37 ("pinctrl: rmobile: Add Renesas RCar pincontrol driver") Signed-off-by: Eugeniu Rosca Acked-by: Marek Vasut --- Changes in v2: - Shorten the summary line - Add "Acked-by: Marek Vasut " --- drivers/pinctrl/renesas/sh_pfc.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index b98c2f185d26..b58e52bbfbb9 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -21,13 +21,13 @@ enum { PINMUX_TYPE_INPUT, }; -#define SH_PFC_PIN_CFG_INPUT (1 << 0) -#define SH_PFC_PIN_CFG_OUTPUT (1 << 1) -#define SH_PFC_PIN_CFG_PULL_UP (1 << 2) -#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) -#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) -#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) -#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) +#define SH_PFC_PIN_CFG_INPUT BIT(0) +#define SH_PFC_PIN_CFG_OUTPUT BIT(1) +#define SH_PFC_PIN_CFG_PULL_UP BIT(2) +#define SH_PFC_PIN_CFG_PULL_DOWN BIT(3) +#define SH_PFC_PIN_CFG_IO_VOLTAGE BIT(4) +#define SH_PFC_PIN_CFG_DRIVE_STRENGTH BIT(5) +#define SH_PFC_PIN_CFG_NO_GPIO BIT(31) struct sh_pfc_pin { u16 pin;