From patchwork Sun Aug 26 13:15:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Angelo Dureghello X-Patchwork-Id: 962248 X-Patchwork-Delegate: jason.jin@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sysam.it Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41ywWq20XCz9s7X for ; Sun, 26 Aug 2018 23:16:18 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 3EF18C21DFF; Sun, 26 Aug 2018 13:16:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E6BACC21D4A; Sun, 26 Aug 2018 13:15:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 68BBDC21D4A; Sun, 26 Aug 2018 13:15:58 +0000 (UTC) Received: from sysam.it (ec2-18-194-220-216.eu-central-1.compute.amazonaws.com [18.194.220.216]) by lists.denx.de (Postfix) with ESMTP id D5FF6C21C27 for ; Sun, 26 Aug 2018 13:15:57 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by sysam.it (Postfix) with ESMTP id E77CE20520; Sun, 26 Aug 2018 13:15:56 +0000 (UTC) Received: from sysam.it ([127.0.0.1]) by localhost (sysam.it [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SvAFKhx7lvqo; Sun, 26 Aug 2018 13:15:56 +0000 (UTC) Received: from localhost.localdomain (host24-218-dynamic.48-82-r.retail.telecomitalia.it [82.48.218.24]) by sysam.it (Postfix) with ESMTPSA id 3DBC72051F; Sun, 26 Aug 2018 13:15:56 +0000 (UTC) From: Angelo Dureghello To: panto@antoniou-consulting.com Date: Sun, 26 Aug 2018 15:15:53 +0200 Message-Id: <20180826131553.13405-1-angelo@sysam.it> X-Mailer: git-send-email 2.18.0 Cc: u-boot@lists.denx.de, Angelo Dureghello Subject: [U-Boot] [PATCH v2] drivers: esdhc: add support for ColdFire mcf5441x family X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch has been tested on the mcf54415-based stmark2 board. The eSDHC driver works reliably using DMA mode. Signed-off-by: Angelo Dureghello --- Changes in v2: - add be to le 32-bit byte swap for ColdFire, - remove HS from host capabilities for ColdFire. --- drivers/mmc/fsl_esdhc.c | 43 ++++++++++++++++++++++++++++++++++++++++- include/fsl_esdhc.h | 1 + 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4528345c67..315c24527d 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -382,6 +382,25 @@ static void check_and_invalidate_dcache_range invalidate_dcache_range(start, end); } +#ifdef CONFIG_MCF5441x +/* + * Swaps 32-bit words to little-endian byte order. + */ +static inline void sd_swap_dma_buff(struct mmc_data *data) +{ + int i, size = data->blocksize >> 2; + u32 *buffer = (u32 *)data->dest; + u32 sw; + + while (data->blocks--) { + for (i = 0; i < size; i++) { + sw = __sw32(*buffer); + *buffer++ = sw; + } + } +} +#endif + /* * Sends a command out on the bus. Takes the mmc pointer, * a command pointer, and an optional data pointer. @@ -538,8 +557,12 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, * cache-fill during the DMA operations such as the * speculative pre-fetching etc. */ - if (data->flags & MMC_DATA_READ) + if (data->flags & MMC_DATA_READ) { check_and_invalidate_dcache_range(cmd, data); +#ifdef CONFIG_MCF5441x + sd_swap_dma_buff(data); +#endif + } #endif } @@ -987,8 +1010,12 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); +#ifdef CONFIG_MCF5441x + esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD); +#else /* Put the PROCTL reg back to the default */ esdhc_write32(®s->proctl, PROCTL_INIT); +#endif /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); @@ -1096,6 +1123,11 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, if (ret) return ret; +#ifdef CONFIG_MCF5441x + /* ColdFire, using SDHC_DATA[3] for card detection */ + esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD); +#endif + #ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); @@ -1120,6 +1152,15 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, voltage_caps = 0; caps = esdhc_read32(®s->hostcapblt); +#ifdef CONFIG_MCF5441x + /* + * MCF5441x RM declares in more points that sdhc clock speed must + * never exceed 25 Mhz. From this, the HS bit needs to be disabled + * from host capabilities. + */ + caps &= ~ESDHC_HOSTCAPBLT_HSS; +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index acd8dd06f8..8dbd5249a7 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -106,6 +106,7 @@ #define PROCTL_INIT 0x00000020 #define PROCTL_DTW_4 0x00000002 #define PROCTL_DTW_8 0x00000004 +#define PROCTL_D3CD 0x00000008 #define CMDARG 0x0002e008