From patchwork Mon Aug 20 00:00:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniu Rosca X-Patchwork-Id: 959470 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="svy3HDtL"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41tvMy09tsz9s4c for ; Mon, 20 Aug 2018 10:10:37 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 69EE9C21C2C; Mon, 20 Aug 2018 00:09:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4A64FC21E16; Mon, 20 Aug 2018 00:07:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4135CC21C93; Mon, 20 Aug 2018 00:04:38 +0000 (UTC) Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by lists.denx.de (Postfix) with ESMTPS id E9F6DC21C2C for ; Mon, 20 Aug 2018 00:04:37 +0000 (UTC) Received: by mail-wm0-f66.google.com with SMTP id o18-v6so12188948wmc.0 for ; Sun, 19 Aug 2018 17:04:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ec3cgJu7d5o91BHwhNJ01D+RM8bj/WtU+6ajzHbcuy4=; b=svy3HDtL7lJ0lT79WNHH9MHQkSLFsDXCRUY9j09aXUTr0igw8SaMtizB2V08GyiMMh IytqTXA5GF93i+cjovXUKt2y7lKWvDmmTPuuvCb2ziadaZn7Ir0TzxvhRPSU1AOkVHJ6 ZJ3gqILyLK2sMjjkxbmN1tyRL7M7ZxZgDm1t9VQiyX4Sczl5R+beYL1tFVSthyy1bbGU GJ1hIIhweTVkWLNbr8oZLChdCXSUQYrV89LOcJr5Spk+kd0W5yFW2eiHBHz3inWIliiS vg/VrMNH+6CVKXhaYrK8HG35gt/q5zZVJJL5rP3IP9GEjObXRy0VP5ReFTMrmzzGG8Rl wbiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ec3cgJu7d5o91BHwhNJ01D+RM8bj/WtU+6ajzHbcuy4=; b=jWBdr88wo25OF/qBSwgOXGafHHad/tI7wlON4mBMDNIWCs5QVitc0heuEcjkk8xVaN G2owpOuWOrh5jl0pX+Yr5t2u08NG0qZEXf/JuXwWrytbrqIxyOeSYldTzqN7Enwo6hlh geqWsbJQ8NxQrJy9hrTC5JmkO6y6q+pLFgky4Ou5+01sglHRueBb44sN5GDC8I4dVkJZ jXj/d1nunGm+nbpBZdLbUUrh3GvkIF1cXwXhkNH2mQ2jqsEr5hiW/qJDsNawqYfYcfPO WmGs2oPufa/CJgO4C8KN1r67uQ9ZM8cNOmyupITnBep+gddN4Prd3rbDTBCrmm0ddZ8O bGsg== X-Gm-Message-State: AOUpUlHOnV+gZq4WyAB84+vD2QoRnBA0SOFDFk/rqwvBqVEtHjprvev4 tpQF1+LsBCdljA2f23OBgRI= X-Google-Smtp-Source: AA+uWPwvCC0r/KhDAmd+H5S/SZx2nGW+UYw509NHz+RFeWCKzYWLgjoy9Xlyqz+sqcwn20cIW7sLxw== X-Received: by 2002:a1c:3743:: with SMTP id e64-v6mr23454469wma.63.1534723477645; Sun, 19 Aug 2018 17:04:37 -0700 (PDT) Received: from localhost.localdomain (ipb218f552.dynamic.kabel-deutschland.de. [178.24.245.82]) by smtp.gmail.com with ESMTPSA id w4-v6sm7648194wro.24.2018.08.19.17.04.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 19 Aug 2018 17:04:36 -0700 (PDT) From: Eugeniu Rosca X-Google-Original-From: Eugeniu Rosca To: Tom Rini , Simon Glass , Masahiro Yamada , Andrey Ryabinin , Andre Przywara , Igor Opaniuk , Rasmus Villemoes , Bryan O'Donoghue , Andy Shevchenko , Chris Packham , Alex Kiernan , Alexey Brodkin , Michal Simek , York Sun , "Derald D . Woods" , Miquel Raynal , Baruch Siach , Albert Aribaud , Stephen Warren , Alexander Graf , Rick Chen , Adam Ford , Simon Goldschmidt , Pantelis Antoniou , Marek Vasut , Takeshi Kihara , Bin Meng , Heinrich Schuchardt , Anatolij Gustschin , Jean-Jacques Hiblot , Jaehoon Chung , Peng Fan , Andy Yan , Philipp Tomsich , Nobuhiro Iwamatsu , Mario Six , Grygorii Strashko , Neil Armstrong , Joe Hershberger , Florian Fainelli , Stefan Roese , Zubair Lutfullah Kakakhel , Quentin Schulz Date: Mon, 20 Aug 2018 02:00:27 +0200 Message-Id: <20180820000033.25519-4-erosca@de.adit-jv.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180820000033.25519-1-erosca@de.adit-jv.com> References: <20180820000033.25519-1-erosca@de.adit-jv.com> X-Mailman-Approved-At: Mon, 20 Aug 2018 00:07:41 +0000 Cc: u-boot@lists.denx.de, Eugeniu Rosca Subject: [U-Boot] [PATCH 3/8] armv8: mmu: Fix "left shift in type int" undefined behavior X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Fix the following UBSAN warnings: ------8<----- CPU: Renesas Electronics R8A7795 rev 2.0 Model: Renesas Salvator-X board based on r8a7795 ES2.0+ ==================================================================== UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:72:9 left shift of 1 by 31 places cannot be represented in type 'int' ==================================================================== ==================================================================== UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:74:9 left shift of 1 by 31 places cannot be represented in type 'int' ==================================================================== ------8<----- While at it, convert to BIT() macro all current "1 << X" shift constructs with X >= 15, which may lead to the same UB, if untreated. Fixes: ad3d6e88a1a4 ("armv8/mmu: Set bits marked RES1 in TCR") Fixes: 9bb367a590fe ("arm64: Disable TTBR1 maps in EL1") Signed-off-by: Eugeniu Rosca --- arch/arm/include/asm/armv8/mmu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 62d00d15c26d..b2ce13db0d2b 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -94,11 +94,11 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) -#define TCR_EPD1_DISABLE (1 << 23) +#define TCR_EPD1_DISABLE BIT(23) -#define TCR_EL1_RSVD (1 << 31) -#define TCR_EL2_RSVD (1 << 31 | 1 << 23) -#define TCR_EL3_RSVD (1 << 31 | 1 << 23) +#define TCR_EL1_RSVD BIT(31) +#define TCR_EL2_RSVD (BIT(31) | BIT(23)) +#define TCR_EL3_RSVD (BIT(31) | BIT(23)) #ifndef __ASSEMBLY__ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)