| Message ID | 20180820000033.25519-4-erosca@de.adit-jv.com |
|---|---|
| State | Superseded |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | Import Undefined Behavior Sanitizer | expand |
On Mon, Aug 20, 2018 at 02:00:27AM +0200, Eugeniu Rosca wrote: > Fix the following UBSAN warnings: > > ------8<----- > CPU: Renesas Electronics R8A7795 rev 2.0 > Model: Renesas Salvator-X board based on r8a7795 ES2.0+ > ==================================================================== > UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:72:9 > left shift of 1 by 31 places cannot be represented in type 'int' > ==================================================================== > ==================================================================== > UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:74:9 > left shift of 1 by 31 places cannot be represented in type 'int' > ==================================================================== > ------8<----- > > While at it, convert to BIT() macro all current "1 << X" shift > constructs with X >= 15, which may lead to the same UB, if untreated. > > Fixes: ad3d6e88a1a4 ("armv8/mmu: Set bits marked RES1 in TCR") > Fixes: 9bb367a590fe ("arm64: Disable TTBR1 maps in EL1") > Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com> > --- > arch/arm/include/asm/armv8/mmu.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h > index 62d00d15c26d..b2ce13db0d2b 100644 > --- a/arch/arm/include/asm/armv8/mmu.h > +++ b/arch/arm/include/asm/armv8/mmu.h > @@ -94,11 +94,11 @@ > #define TCR_TG0_4K (0 << 14) > #define TCR_TG0_64K (1 << 14) > #define TCR_TG0_16K (2 << 14) > -#define TCR_EPD1_DISABLE (1 << 23) > +#define TCR_EPD1_DISABLE BIT(23) > > -#define TCR_EL1_RSVD (1 << 31) > -#define TCR_EL2_RSVD (1 << 31 | 1 << 23) > -#define TCR_EL3_RSVD (1 << 31 | 1 << 23) > +#define TCR_EL1_RSVD BIT(31) > +#define TCR_EL2_RSVD (BIT(31) | BIT(23)) > +#define TCR_EL3_RSVD (BIT(31) | BIT(23)) > > #ifndef __ASSEMBLY__ > static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) For consistency within the file, spell it out as 1UL ? I don't like mixing shifts and BITS in a file, and I really don't like being inconsistent, so I'd also be OK with BIT() in all of the bits.
Hi Tom, On Sun, Aug 19, 2018 at 09:51:42PM -0400, Tom Rini wrote: > On Mon, Aug 20, 2018 at 02:00:27AM +0200, Eugeniu Rosca wrote: [..] > > diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h > > index 62d00d15c26d..b2ce13db0d2b 100644 > > --- a/arch/arm/include/asm/armv8/mmu.h > > +++ b/arch/arm/include/asm/armv8/mmu.h > > @@ -94,11 +94,11 @@ > > #define TCR_TG0_4K (0 << 14) > > #define TCR_TG0_64K (1 << 14) > > #define TCR_TG0_16K (2 << 14) > > -#define TCR_EPD1_DISABLE (1 << 23) > > +#define TCR_EPD1_DISABLE BIT(23) > > > > -#define TCR_EL1_RSVD (1 << 31) > > -#define TCR_EL2_RSVD (1 << 31 | 1 << 23) > > -#define TCR_EL3_RSVD (1 << 31 | 1 << 23) > > +#define TCR_EL1_RSVD BIT(31) > > +#define TCR_EL2_RSVD (BIT(31) | BIT(23)) > > +#define TCR_EL3_RSVD (BIT(31) | BIT(23)) > > > > #ifndef __ASSEMBLY__ > > static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) > > For consistency within the file, spell it out as 1UL ? I don't like > mixing shifts and BITS in a file, and I really don't like being > inconsistent, so I'd also be OK with BIT() in all of the bits. I will use (1UL << i) in v2, unless there is some strong preference to use BIT() macro. In the latter case, a simple definition like (7 << N) will require conversion to (BIT(N+2) | BIT(N+1) | BIT(N)), which looks more complicated to me. > -- > Tom Thanks, Eugeniu.
==================================================================== UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:72:9 left shift of 1 by 31 places cannot be represented in type 'int' ==================================================================== ==================================================================== UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:74:9 left shift of 1 by 31 places cannot be represented in type 'int' ==================================================================== ------8<----- While at it, convert to BIT() macro all current "1 << X" shift constructs with X >= 15, which may lead to the same UB, if untreated. Fixes: ad3d6e88a1a4 ("armv8/mmu: Set bits marked RES1 in TCR") Fixes: 9bb367a590fe ("arm64: Disable TTBR1 maps in EL1") Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com> --- arch/arm/include/asm/armv8/mmu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 62d00d15c26d..b2ce13db0d2b 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -94,11 +94,11 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) -#define TCR_EPD1_DISABLE (1 << 23) +#define TCR_EPD1_DISABLE BIT(23) -#define TCR_EL1_RSVD (1 << 31) -#define TCR_EL2_RSVD (1 << 31 | 1 << 23) -#define TCR_EL3_RSVD (1 << 31 | 1 << 23) +#define TCR_EL1_RSVD BIT(31) +#define TCR_EL2_RSVD (BIT(31) | BIT(23)) +#define TCR_EL3_RSVD (BIT(31) | BIT(23)) #ifndef __ASSEMBLY__ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)