From patchwork Mon Jun 25 10:34:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 934150 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GSPX0RZv"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41Dltc6Zbcz9rvt for ; Mon, 25 Jun 2018 20:35:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 86358C21E1E; Mon, 25 Jun 2018 10:35:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 73CCCC21C93; Mon, 25 Jun 2018 10:35:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3BDD2C21C93; Mon, 25 Jun 2018 10:35:11 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id 8EC85C21C8B for ; Mon, 25 Jun 2018 10:35:10 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id y8-v6so6246138pfm.10 for ; Mon, 25 Jun 2018 03:35:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=ydL39Jl3cdNTwWCNdORNGvVJ/4Qjj/881mk4ZVbP5MM=; b=GSPX0RZvMV6duEXgz2em373R5bmVY/rqPQL2MO4Qbx0T52dqZJJq9a+qnQSg21RBdO 9K4+SyDUugmpdCqVHvdUwCFZxzDS6pNwrR62E6GMFDxbuJxOenYekq71UcgtjGdL/BCC rpZq81j9J6hLjKWvuDDkDBQAv60jyJD+eOcVjO9qk9iliykUOj1FL+HyDp9Fz2iERAHC KWJeSIMYU3RcQoNCAa9XPsU8ncb6/PXmbJrQ7RWUxkosAuKEPSmaBxwmDvX5+w0Kq4Ri GYgUQTDkChqeMOI11BuQwEW/jCgFMwf/T2sKc8I6b1rx1iSBe+QR2cvjFoUV56XC7hbq wjzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ydL39Jl3cdNTwWCNdORNGvVJ/4Qjj/881mk4ZVbP5MM=; b=embiOROzVuzX14+AbZj4K7+vP+B+UmW7InnI0AeC2lqx/OJ9Lc1UXyKh0ewS/yeZuq 9GRVm9BDgzewijxF17DFSilEgCzEbC0GKp5inPa0J7A1XweIevcIwSeaschuxloREN6L kFTMHhS2XJuiIqCWejGQKPkxdTTrAA8hOmIK4JsmNiYflSh3Dh7KuFSW9SKM1b0lSGda MHMDtrl7ec08CSDXN7UCE3axeIeWHclKl6P4Jr4a0DCqIVsW2JhjkckiI9SwoXMIKVRO Eaxe7+q4OiSRXVuy2jYb4pJQUagDAVKd65K1NABZzLtq78hkMLuQDVXHc3ohuEMk3UW8 h3wA== X-Gm-Message-State: APt69E02xnAXQl9lhG/caiBnzUElUHuDBHsV2TDo08SmXH3ZnYBeZ1L6 viybUoBJhHg0nGWSMxvGnVY1R5M4 X-Google-Smtp-Source: ADUXVKJWaRX/BBwQH4JG5zK7lZQLpu13HkSGaVi2C/L6ZX5cQLHqh+gZI+qFe+GM2eIwHBRVbEgjJQ== X-Received: by 2002:a63:a401:: with SMTP id c1-v6mr10188800pgf.147.1529922908596; Mon, 25 Jun 2018 03:35:08 -0700 (PDT) Received: from chrisp-dl.ws.atlnz.lc ([2001:df5:b000:22:3a2c:4aff:fe70:2b02]) by smtp.gmail.com with ESMTPSA id v15-v6sm20425363pff.120.2018.06.25.03.35.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 25 Jun 2018 03:35:07 -0700 (PDT) From: Chris Packham To: u-boot@lists.denx.de Date: Mon, 25 Jun 2018 22:34:56 +1200 Message-Id: <20180625103457.8674-1-judge.packham@gmail.com> X-Mailer: git-send-email 2.18.0 Cc: Alexandru Gagniuc , Stefan Mavrodiev , Michal Simek , Joe Hershberger , Chris Packham Subject: [U-Boot] [PATCH 1/2] net: mv88e61xx: add configuration for RGMII delay X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some hardware designs connect a CPU MAC directly to the RGMII interface of a mv88e61xx device. On such devices a delay on the RX/TX lines is required, this can either be achieved by adding extra length to the traces on the PCB or by implementing the delay in silicon. This is an implementation of the latter. Signed-off-by: Chris Packham --- drivers/net/phy/Kconfig | 4 ++++ drivers/net/phy/mv88e61xx.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f5821dfed96d..98cd57eea977 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -59,6 +59,10 @@ config MV88E61XX_PHY_PORTS config MV88E61XX_FIXED_PORTS hex "Bitmask of PHYless serdes Ports" +config MV88E61XX_RGMII_DELAY + bool "Add delay to RGMII outputs" + default n + endif # MV88E61XX_SWITCH config PHYLIB_10G diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index ea54a1531053..d258ba1ef0f3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -69,6 +69,7 @@ #define PORT_REG_CTRL 0x04 #define PORT_REG_VLAN_MAP 0x06 #define PORT_REG_VLAN_ID 0x07 +#define PORT_REG_RGMII_TIMING 0x1A /* Phy registers */ #define PHY_REG_CTRL1 0x10 @@ -122,6 +123,9 @@ #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11 +#define PORT_REG_RGMII_TIMING_RX_DELAY BIT(10) +#define PORT_REG_RGMII_TIMING_TX_DELAY BIT(9) + #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10) #define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8 @@ -705,6 +709,24 @@ unforce: return res; } +static int mv88e61xx_rgmii_timing_cfg(struct phy_device *phydev) +{ +#ifdef CONFIG_MV88E61XX_RGMII_DELAY + int val; + + val = mv88e61xx_port_read(phydev, 6, PORT_REG_RGMII_TIMING); + if (val < 0) + return val; + + val |= PORT_REG_RGMII_TIMING_RX_DELAY | + PORT_REG_RGMII_TIMING_TX_DELAY; + + return mv88e61xx_port_write(phydev, 6, PORT_REG_RGMII_TIMING, val); +#else + return 0; +#endif +} + static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) { int val; @@ -774,6 +796,10 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev) return val; } } else { + val = mv88e61xx_rgmii_timing_cfg(phydev); + if (val < 0) + return val; + val = mv88e61xx_fixed_port_setup(phydev, CONFIG_MV88E61XX_CPU_PORT); if (val < 0)