From patchwork Wed May 16 09:13:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 914285 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eJneqm3F"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40m83l6W8Yz9s2L for ; Wed, 16 May 2018 19:17:55 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 92098C21E29; Wed, 16 May 2018 09:16:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8FC8BC21E16; Wed, 16 May 2018 09:14:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 90B71C21DB6; Wed, 16 May 2018 09:14:25 +0000 (UTC) Received: from mail-wr0-f194.google.com (mail-wr0-f194.google.com [209.85.128.194]) by lists.denx.de (Postfix) with ESMTPS id 450E0C21DB6 for ; Wed, 16 May 2018 09:14:17 +0000 (UTC) Received: by mail-wr0-f194.google.com with SMTP id p5-v6so52647wre.12 for ; Wed, 16 May 2018 02:14:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NUAcMQ/N/UI4bmbbok+TEUwYVY8glc67cjCGoR00pJ4=; b=eJneqm3FmsSUN8VfeEM2iuXCT2w1JGbWdWcZIhxgwLE8WV4dX5W18Gj8M6sWYxjvmS c1MSlunv+DsIdXOrkb82rmyZ5+BrfQZnrMGYxV4smEMAX09nWegJd5OXq4W5erl9VT0+ dzE6/2Dz6ggwBcOOeJojFZMFskWF9/4W1e7jTWINT4xYp5e5MhpwPvI/vWrXPKYnY+UI yQ/0CeL78yNOqs1NUJDGm8R7VN4eTjRYW5IVkd/zjt96Uj9OBn3EPzneBk2tS0/UZjYJ CUX3ejMh+kIp/hd7tUm5Sehala0tcHwwBjvvwDKEaVZARj1nRG8X66j8KwNgVnwahpuJ 8fWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NUAcMQ/N/UI4bmbbok+TEUwYVY8glc67cjCGoR00pJ4=; b=X5C+jdnQucM1Q8ipGtMS348/IreKaka87BOrNu7jok66JajM32bgRHrUv9kNymUFom NM/KHiIZLjsEjGYZO+1QacgMDEOowPZhGcHo6E3/eFt28n6rXTfeFf+x8I/p6pryl6yk BFF4ki3aT1PmkpaxECgVT2zZYzTO9yu0YYeSjTLZyFGbhsbcQ5WELlRlk+Zt8rB1TQnN E96ewbiKbhFknlslgRMJy9Jg1YHyHiknLwMHALq7UpXwurjEOdZigcDFIq44cCLz/O55 dFrjvilnYyr/cBCPJ3GWK+pSgRnl7RNMwE8NhMjfsidoBqe3FvDsqGRZ5e64SaREA2Yx r5Rw== X-Gm-Message-State: ALKqPwcTH3lHdvd4QI/acGf9pCQdlDq5z3+MPFKur2wucTUkrgk91vA4 a/BHKk9JGZe5wUhMP0TBTZmfjxYV//Y= X-Google-Smtp-Source: AB8JxZonueVZkuihbbXmRCUmRlE30M1JPNl7R5cRJQxhqe0JmmYfrMmk5bp3+tIOVmaGGUxq1L9a9Q== X-Received: by 2002:adf:e38e:: with SMTP id e14-v6mr62589wrm.198.1526462056869; Wed, 16 May 2018 02:14:16 -0700 (PDT) Received: from localhost.localdomain ([141.226.166.38]) by smtp.gmail.com with ESMTPSA id h12-v6sm1920655wmc.7.2018.05.16.02.14.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 May 2018 02:14:16 -0700 (PDT) From: Ramon Fried To: albert.u.boot@aribaud.net, mateusz.kulikowski@gmail.com, jramirez@baylibre.com, robdclark@gmail.com, sjg@chromium.org Date: Wed, 16 May 2018 12:13:40 +0300 Message-Id: <20180516091342.7509-5-ramon.fried@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180516091342.7509-1-ramon.fried@gmail.com> References: <20180516091342.7509-1-ramon.fried@gmail.com> Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 5/7] mach-snapdragon: Introduce pinctrl driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds pinmux and pinctrl driver for TLMM subsystem in snapdragon chipsets. Currently, supporting only 8016, but implementation is generic and 8096 can be added easily. Driver is using the generic dt-bindings and doesn't introduce any new bindings (yet). Signed-off-by: Ramon Fried Reviewed-by: Simon Glass --- v2: * restructred the code to be more generic * Reduced pin table size by snprintf on runtime as suggested by Simon. arch/arm/mach-snapdragon/Makefile | 2 + arch/arm/mach-snapdragon/pinctrl-apq8016.c | 62 +++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 128 ++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 29 ++++ configs/dragonboard410c_defconfig | 5 + .../dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 +++ 6 files changed, 248 insertions(+) create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 1c23dc52cf..1d35fea912 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -6,4 +6,6 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o +obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o obj-y += clock-snapdragon.o diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8016.c b/arch/arm/mach-snapdragon/pinctrl-apq8016.c new file mode 100644 index 0000000000..602af1b1d3 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-apq8016.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm APQ8016 pinctrl + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include "pinctrl-snapdragon.h" +#include + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN]; +static const char * const msm_pinctrl_pins[] = { + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", + "QDSD_CLK", + "QDSD_CMD", + "QDSD_DATA0", + "QDSD_DATA1", + "QDSD_DATA2", + "QDSD_DATA3", +}; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp1_uart", 2}, +}; + +static const char *apq8016_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *apq8016_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector < 130) { + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; + } else { + return msm_pinctrl_pins[selector - 130]; + } +} + +static unsigned int apq8016_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data apq8016_data = { + .pin_count = 140, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = apq8016_get_function_name, + .get_function_mux = apq8016_get_function_mux, + .get_pin_name = apq8016_get_pin_name, +}; + diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c new file mode 100644 index 0000000000..9b7cf59a67 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TLMM driver for Qualcomm APQ8016, APQ8096 + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#include +#include +#include +#include +#include +#include "pinctrl-snapdragon.h" + +struct msm_pinctrl_priv { + phys_addr_t base; + struct msm_pinctrl_data *data; +}; + +#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_ENABLE BIT(9) + +static const struct pinconf_param msm_conf_params[] = { + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, +}; + +static int msm_get_functions_count(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->functions_count; +} + +static int msm_get_pins_count(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->pin_count; +} + +static const char *msm_get_function_name(struct udevice *dev, + unsigned int selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->get_function_name(dev, selector); +} + +static int msm_pinctrl_probe(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + priv->base = devfdt_get_addr(dev); + priv->data = (struct msm_pinctrl_data *)dev->driver_data; + + return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; +} + +static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->get_pin_name(dev, selector); +} + +static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, + unsigned int func_selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE, + priv->data->get_function_mux(func_selector) << 2); + return 0; +} + +static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH: + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_DRV_STRENGTH_MASK, argument << 6); + break; + case PIN_CONFIG_BIAS_DISABLE: + clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_GPIO_PULL_MASK); + break; + default: + return 0; + } + + return 0; +} + +static struct pinctrl_ops msm_pinctrl_ops = { + .get_pins_count = msm_get_pins_count, + .get_pin_name = msm_get_pin_name, + .set_state = pinctrl_generic_set_state, + .pinmux_set = msm_pinmux_set, + .pinconf_num_params = ARRAY_SIZE(msm_conf_params), + .pinconf_params = msm_conf_params, + .pinconf_set = msm_pinconf_set, + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data }, + { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, + { } +}; + +U_BOOT_DRIVER(pinctrl_snapdraon) = { + .name = "pinctrl_msm", + .id = UCLASS_PINCTRL, + .of_match = msm_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv), + .ops = &msm_pinctrl_ops, + .probe = msm_pinctrl_probe, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h new file mode 100644 index 0000000000..6fd9971f17 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm Pin control + * + * (C) Copyright 2018 Ramon Fried + * + */ +#ifndef _PINCTRL_SNAPDRAGON_H +#define _PINCTRL_SNAPDRAGON_H + +#include + +struct msm_pinctrl_data { + int pin_count; + int functions_count; + const char *(*get_function_name)(struct udevice *dev, + unsigned int selector); + unsigned int (*get_function_mux)(unsigned int selector); + const char *(*get_pin_name)(struct udevice *dev, + unsigned int selector); +}; + +struct pinctrl_function { + const char *name; + int val; +}; + +extern struct msm_pinctrl_data apq8016_data; + +#endif diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index e6114db2ce..4b3de64dd5 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -45,3 +45,8 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_FULL=y +CONFIG_PINCTRL_GENERIC=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h new file mode 100644 index 0000000000..615affb6f2 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides constants for Qualcomm Snapdragon pinctrl bindings. + * + * (C) Copyright 2018 Ramon Fried + * + */ + +#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H +#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H + +/* GPIO Drive Strength */ +#define DRIVE_STRENGTH_2MA 0 +#define DRIVE_STRENGTH_4MA 1 +#define DRIVE_STRENGTH_6MA 2 +#define DRIVE_STRENGTH_8MA 3 +#define DRIVE_STRENGTH_10MA 4 +#define DRIVE_STRENGTH_12MA 5 +#define DRIVE_STRENGTH_14MA 6 +#define DRIVE_STRENGTH_16MA 7 + +#endif