From patchwork Wed Mar 7 21:52:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882818 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="gHZ1+/M/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSGD6BSpz9sgw for ; Thu, 8 Mar 2018 08:59:00 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 862CDC21F1F; Wed, 7 Mar 2018 21:57:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0B89CC21FCD; Wed, 7 Mar 2018 21:55:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3829DC21E62; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id 930A1C21BE5 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 4FFCB62654; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=/4CElCPACgzCfveeqP9EArTCiHFN+VulA4M0LvjrzEI=; h=From:To:Date; b=gHZ1+/M/D++N2talRz2xIHuG1AbjBvLGB0zvhYi4nw0BaNRiag10tbdbhij8C+Rnn leQje2ginHScIiKe4D/mZl++16kbYPR3LtXmQT7XSQpQ2Y/w2vMYZH9RlCJRqEDUDW 8n1RWeab653Q3GSz9rRTSDu7aJYEgi88dqAD7k64= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:04 +0100 Message-Id: <20180307215216.10418-8-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 07/19] phy: marvell: a3700: Access USB3 register indirectly on lane 2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When USB3 is on comphy lane 2 on the Armada 37xx, the registers have to be accessed indirectly via SATA indirect access. Signed-off-by: Marek Behun --- drivers/phy/marvell/comphy_a3700.c | 111 +++++++++++++++++++++++++------------ drivers/phy/marvell/comphy_a3700.h | 1 + 2 files changed, 78 insertions(+), 34 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 81d24a5b61..b5f2013bbb 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -133,7 +133,7 @@ static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type) */ static int comphy_pcie_power_up(u32 speed, u32 invert) { - int ret; + int ret; debug_enter(); @@ -300,17 +300,50 @@ static int comphy_sata_power_up(void) return ret; } +/* + * usb3_reg_set16_indirect + * + * return: void + */ +static void usb3_reg_set16_indirect(u32 reg, u16 data, u16 mask) +{ + reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data, mask); +} + +/* + * usb3_reg_set16_direct + * + * return: void + */ +static void usb3_reg_set16_direct(u32 reg, u16 data, u16 mask) +{ + reg_set16(PHY_ADDR(USB3, reg), data, mask); +} + /* * comphy_usb3_power_up * * return: 1 if PLL locked (OK), 0 otherwise (FAIL) */ -static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) +static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) { - int ret; + int ret; + void (*usb3_reg_set16)(u32, u16, u16); debug_enter(); + /* + * When Lane 2 PHY is for USB3, access the PHY registers + * through indirect Address and Data registers INDIR_ACC_PHY_ADDR + * (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]) + * within the SATA Host Controller registers, Lane 2 base register + * offset is 0x200 + */ + if (lane == 2) + usb3_reg_set16 = usb3_reg_set16_indirect; + else + usb3_reg_set16 = usb3_reg_set16_direct; + /* * 1. Power up OTG module */ @@ -325,38 +358,38 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) /* 0xd005c300 = 0x1001 */ /* set PRD_TXDEEMPH (3.5db de-emph) */ - reg_set16(PHY_ADDR(USB3, LANE_CFG0), 0x1, 0xFF); + usb3_reg_set16(LANE_CFG0, 0x1, 0xFF); /* * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in - * low impedance mode during electrical idle + * low impedance mode during electrical idle + * unset BIT4: set G2 Tx Datapath with no Delayed Latency + * unset BIT6: set Tx Detect Rx Mode at LoZ mode */ - /* unset BIT4: set G2 Tx Datapath with no Delayed Latency */ - /* unset BIT6: set Tx Detect Rx Mode at LoZ mode */ - reg_set16(PHY_ADDR(USB3, LANE_CFG1), 0x0, 0xFFFF); + usb3_reg_set16(LANE_CFG1, 0x0, 0xFFFF); - /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ - reg_set16(PHY_ADDR(USB3, LANE_CFG4), bf_spread_spectrum_clock_en, 0x80); + /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */ + usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80); /* * set Override Margining Controls From the MAC: Use margining signals * from lane configuration */ - reg_set16(PHY_ADDR(USB3, TEST_MODE_CTRL), rb_mode_margin_override, 0xFFFF); + usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF); /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ /* set Mode Clock Source = PCLK is generated from REFCLK */ - reg_set16(PHY_ADDR(USB3, GLOB_CLK_SRC_LO), 0x0, 0xFF); + usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF); /* set G2 Spread Spectrum Clock Amplitude at 4K */ - reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_2), g2_tx_ssc_amp, 0xF000); + usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000); /* * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register * Master Current Select */ - reg_set16(PHY_ADDR(USB3, GEN2_SETTINGS_3), 0x0, 0xFFFF); + usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF); /* * 3. Check crystal jumper setting and program the Power and PLL @@ -364,62 +397,71 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) */ if (get_ref_clk() == 40) { /* 40 MHz */ - reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA3, 0xFFFF); + usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF); } else { /* 25 MHz */ - reg_set16(PHY_ADDR(USB3, PWR_PLL_CTRL), 0xFCA2, 0xFFFF); + usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF); } /* * 4. Change RX wait */ - reg_set16(PHY_ADDR(USB3, PWR_MGM_TIM1), 0x10C, 0xFFFF); + usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF); /* * 5. Enable idle sync */ - reg_set16(PHY_ADDR(USB3, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); + usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF); /* * 6. Enable the output of 500M clock */ - reg_set16(PHY_ADDR(USB3, MISC_REG0), 0xA00D | rb_clk500m_en, 0xFFFF); + usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF); /* * 7. Set 20-bit data width */ - reg_set16(PHY_ADDR(USB3, DIG_LB_EN), 0x0400, 0xFFFF); + usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF); /* * 8. Override Speed_PLL value and use MAC PLL */ - reg_set16(PHY_ADDR(USB3, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, - 0xFFFF); + usb3_reg_set16(KVCO_CAL_CTRL, 0x0040 | rb_use_max_pll_rate, 0xFFFF); /* * 9. Check the Polarity invert bit */ if (invert & PHY_POLARITY_TXD_INVERT) - reg_set16(PHY_ADDR(USB3, SYNC_PATTERN), phy_txd_inv, 0); + usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0); if (invert & PHY_POLARITY_RXD_INVERT) - reg_set16(PHY_ADDR(USB3, SYNC_PATTERN), phy_rxd_inv, 0); + usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0); /* * 10. Release SW reset */ - reg_set16(PHY_ADDR(USB3, GLOB_PHY_CTRL0), - rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20, - 0xFFFF); + usb3_reg_set16(GLOB_PHY_CTRL0, + rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 + | 0x20, 0xFFFF); /* Wait for > 55 us to allow PCLK be enabled */ udelay(PLL_SET_DELAY_US); /* Assert PCLK enabled */ - ret = comphy_poll_reg(PHY_ADDR(USB3, LANE_STAT1), /* address */ - rb_txdclk_pclk_en, /* value */ - rb_txdclk_pclk_en, /* mask */ - POLL_16B_REG); /* 16bit */ + if (lane == 2) { + reg_set(rh_vsreg_addr, + LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET, + 0xFFFFFFFF); + ret = comphy_poll_reg(rh_vsreg_data, /* address */ + rb_txdclk_pclk_en, /* value */ + rb_txdclk_pclk_en, /* mask */ + POLL_32B_REG); /* 32bit */ + } else { + ret = comphy_poll_reg(PHY_ADDR(USB3, LANE_STAT1), /* address */ + rb_txdclk_pclk_en, /* value */ + rb_txdclk_pclk_en, /* mask */ + POLL_16B_REG); /* 16bit */ + } if (!ret) printf("Failed to lock USB3 PLL\n"); @@ -455,7 +497,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert) */ static int comphy_usb2_power_up(u8 usb32) { - int ret; + int ret; debug_enter(); @@ -620,7 +662,7 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) */ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) { - int ret; + int ret; debug_enter(); @@ -906,7 +948,8 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, case PHY_TYPE_USB3_HOST0: case PHY_TYPE_USB3_DEVICE: - ret = comphy_usb3_power_up(comphy_map->type, + ret = comphy_usb3_power_up(lane, + comphy_map->type, comphy_map->speed, comphy_map->invert); break; diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 5031c25eb1..772e86515a 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -60,6 +60,7 @@ #define USB2PHY2_BASE MVEBU_REG(0x05F000) #define USB32_CTRL_BASE MVEBU_REG(0x05D800) #define USB3PHY_SHFT 2 +#define USB3PHY_LANE2_REG_BASE_OFFSET 0x200 static inline void __iomem *SGMIIPHY_ADDR(u32 lane, u32 addr) {