From patchwork Wed Mar 7 21:52:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882819 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="u6Q/kwnR"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSH213Wyz9sgw for ; Thu, 8 Mar 2018 08:59:41 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id AD505C21F21; Wed, 7 Mar 2018 21:57:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 18F2DC21FD4; Wed, 7 Mar 2018 21:55:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4F994C21E3A; Wed, 7 Mar 2018 21:55:04 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id DA3DCC21E5B for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 9EAA0626A2; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=/L2DPNE7b7WOj+02M1Z3cEmFq+gLldWslO/epBnn4+c=; h=From:To:Date; b=u6Q/kwnRDrAcqWcd1JcMJFk+IYLy/kSLb1CTGI2HeWa6f1toIuR2qZrawae6RKvK/ /BHEmXNe7XwgvYZyVxSWCd27sKTwVEbwN+k/7KOGjbz/cWdMW1nQqq4wALen9m6UXJ kzndVTiGBsa+Dqgci0yw2H9OhkrSRiUVHXEgUqGc= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:09 +0100 Message-Id: <20180307215216.10418-13-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 12/19] phy: marvell: a3700: Save/restore selector reg in SGMII init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In SGMII initialization PIN_PIPE_SEL has to be zero when resetting the PHY. Since comphy_mux already set the selector register to correct values, we have to store it's value before setting it to 0 and restore it after SGMII init. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 9 ++++++++- drivers/phy/marvell/comphy_a3700.h | 1 - 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index c665d6fde8..71245b766f 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -708,13 +708,15 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) { int ret; + u32 saved_selector; debug_enter(); /* * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0 */ - reg_set(COMPHY_SEL_ADDR, 0, rf_compy_select(lane)); + saved_selector = readl(COMPHY_SEL_ADDR); + reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF); /* * 2. Reset PHY by setting PHY input port PIN_RESET=1. @@ -885,6 +887,11 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) if (!ret) printf("Failed to init RX of SGMII PHY %d\n", lane); + /* + * Restore saved selector. + */ + reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF); + debug_exit(); return ret; diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index ef55f719b9..b674ef9064 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -23,7 +23,6 @@ * COMPHY SB definitions */ #define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC) -#define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0)) #define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28) #define rb_pin_pu_iveref BIT(1)