From patchwork Wed Mar 7 21:52:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 882816 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nic.cz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=nic.cz header.i=@nic.cz header.b="E8b7scLI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxSG11MtZz9sgy for ; Thu, 8 Mar 2018 08:58:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 32F99C21E62; Wed, 7 Mar 2018 21:58:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 439C5C21F47; Wed, 7 Mar 2018 21:55:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6FEABC21C4A; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from mail.nic.cz (mail.nic.cz [217.31.204.67]) by lists.denx.de (Postfix) with ESMTPS id BF89CC21DB6 for ; Wed, 7 Mar 2018 21:55:03 +0000 (UTC) Received: from dellmb.labs.office.nic.cz (unknown [IPv6:2001:1488:fffe:6:8982:ed8c:62b1:c0c8]) by mail.nic.cz (Postfix) with ESMTP id 7CBB16267E; Wed, 7 Mar 2018 22:55:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=nic.cz; s=default; t=1520459703; bh=GJ4Q39zdOgONxVjV5Mx+2jW6b1V42gZOSOGLs66THGE=; h=From:To:Date; b=E8b7scLIbTycLdqoBY6qHOJHYCURDKOg9WKdWaAG0y+VxkKCauKLlBCGrirJNUcOO Os6nHX1MpuxnADyi/DL4E2FpoZuidv0sIu5N3vJDrw5VPYO4074VYlfXhXVn7K4VPh 9wdASc9LtDviUOK2+i7GUOK2zZQiYQsmfdLBud3g= From: =?utf-8?q?Marek_Beh=C3=BAn?= To: u-boot@lists.denx.de Date: Wed, 7 Mar 2018 22:52:07 +0100 Message-Id: <20180307215216.10418-11-marek.behun@nic.cz> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180307215216.10418-1-marek.behun@nic.cz> References: <20180307215216.10418-1-marek.behun@nic.cz> X-Virus-Scanned: clamav-milter 0.99.2 at mail X-Virus-Status: Clean Cc: Tomas Hlavacek , Stefan Roese Subject: [U-Boot] [PATCH v1 10/19] phy: marvell: mux: Support nontrivial node order in selector register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently comphy_mux supports only trivial order of nodes in pin selector register, that is lane N on position N*bitcount. Add support for nontrivial order, with map stored in device tree property mux-lane-order. This is needed for Armada 37xx. Signed-off-by: Marek Behun --- drivers/phy/marvell/comphy.h | 1 + drivers/phy/marvell/comphy_core.c | 4 ++++ drivers/phy/marvell/comphy_mux.c | 15 ++++++++++++--- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h index c9b94a4c5e..32e0a1e652 100644 --- a/drivers/phy/marvell/comphy.h +++ b/drivers/phy/marvell/comphy.h @@ -97,6 +97,7 @@ struct chip_serdes_phy_config { void __iomem *hpipe3_base_addr; u32 comphy_lanes_count; u32 comphy_mux_bitcount; + const fdt32_t *comphy_mux_lane_order; u32 cp_index; }; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 426db30f73..1e5664c435 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -135,6 +135,10 @@ static int comphy_probe(struct udevice *dev) return -EINVAL; } + chip_cfg->comphy_mux_lane_order = + fdtdec_locate_array(blob, node, "mux-lane-order", + chip_cfg->comphy_lanes_count); + if (device_is_compatible(dev, "marvell,comphy-armada-3700")) chip_cfg->ptr_comphy_chip_init = comphy_a3700_init; diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index b036fb13b9..a8b07fdc98 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -79,7 +79,8 @@ static u32 comphy_mux_get_mux_value(struct comphy_mux_data *mux_data, static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, struct comphy_map *comphy_map_data, int comphy_max_lanes, - void __iomem *selector_base, u32 bitcount) + void __iomem *selector_base, + const fdt32_t *mux_lane_order, u32 bitcount) { u32 lane, value, offset, mask; @@ -90,7 +91,13 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, if (comphy_map_data->type == PHY_TYPE_IGNORE) continue; - offset = lane * bitcount; + /* if the order of nodes in selector base register is + nontrivial, use mapping from mux_lane_order */ + if (mux_lane_order) + offset = fdt32_to_cpu(mux_lane_order[lane]) * bitcount; + else + offset = lane * bitcount; + mask = (((1 << bitcount) - 1) << offset); value = (comphy_mux_get_mux_value(mux_data, comphy_map_data->type, @@ -106,6 +113,7 @@ void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg, void __iomem *selector_base) { struct comphy_mux_data *mux_data; + const fdt32_t *mux_lane_order; u32 mux_bitcount; u32 comphy_max_lanes; @@ -113,13 +121,14 @@ void comphy_mux_init(struct chip_serdes_phy_config *chip_cfg, comphy_max_lanes = chip_cfg->comphy_lanes_count; mux_data = chip_cfg->mux_data; + mux_lane_order = chip_cfg->comphy_mux_lane_order; mux_bitcount = chip_cfg->comphy_mux_bitcount; /* check if the configuration is valid */ comphy_mux_check_config(mux_data, comphy_map_data, comphy_max_lanes); /* Init COMPHY selectors */ comphy_mux_reg_write(mux_data, comphy_map_data, comphy_max_lanes, - selector_base, mux_bitcount); + selector_base, mux_lane_order, mux_bitcount); debug_exit(); }