| Message ID | 20180207193526.48434-2-icenowy@aosc.io |
|---|---|
| State | Changes Requested |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | Add 3GiB DRAM support to 64-bit Allwinner SoCs | expand |
On 07/02/18 19:35, Icenowy Zheng wrote: Hi, > All Allwinner 64-bit SoCs now are known to be able to access 3GiB of > external DRAM, however the size of DRAM part in the MMU translation > table is still 2GiB. > > Change the size of DRAM part in MMU table to 3GiB. This is needed for the (new) get_ram_size() to work, isn't it? I don't like this routine very much, but I guess this change here is fine anyway: Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre. > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > arch/arm/mach-sunxi/board.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c > index 0c60ee04da..4ee1040ac9 100644 > --- a/arch/arm/mach-sunxi/board.c > +++ b/arch/arm/mach-sunxi/board.c > @@ -53,7 +53,7 @@ static struct mm_region sunxi_mem_map[] = { > /* RAM */ > .virt = 0x40000000UL, > .phys = 0x40000000UL, > - .size = 0x80000000UL, > + .size = 0xC0000000UL, > .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | > PTE_BLOCK_INNER_SHARE > }, { >
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 0c60ee04da..4ee1040ac9 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -53,7 +53,7 @@ static struct mm_region sunxi_mem_map[] = { /* RAM */ .virt = 0x40000000UL, .phys = 0x40000000UL, - .size = 0x80000000UL, + .size = 0xC0000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, {
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of external DRAM, however the size of DRAM part in the MMU translation table is still 2GiB. Change the size of DRAM part in MMU table to 3GiB. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- arch/arm/mach-sunxi/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)