From patchwork Thu Jan 18 04:16:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 862746 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fVh8G6XW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zMW181fPZz9t2Q for ; Thu, 18 Jan 2018 15:18:52 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DE180C21E3A; Thu, 18 Jan 2018 04:17:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0BCD2C21E28; Thu, 18 Jan 2018 04:17:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 45D15C21E39; Thu, 18 Jan 2018 04:16:41 +0000 (UTC) Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by lists.denx.de (Postfix) with ESMTPS id 54338C21E26 for ; Thu, 18 Jan 2018 04:16:36 +0000 (UTC) Received: by mail-pg0-f65.google.com with SMTP id r19so7196476pgn.1 for ; Wed, 17 Jan 2018 20:16:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BtnIUN6X03hb8vh/PGbquJxO/yPNj/iG0JhEY8dFMbU=; b=fVh8G6XWVEMuYkXCJy8e2Gw5N0hs2h31iBm0MbnVsF500VkcDkJtlmHsAO/LOViKoP OW82B32EiehbO7OvHvHDuSov9kJq0JPXJL2mAHZ6BT3lNHswcvmeAh9OHnWZqjdd6rtb vbMg2gIozVy9ODHMKXdHnf5k6bq0tCWvC97jEBWI4KRQd3NdleSqUD32Q7fZ7oMDLkbi DdD4yVNme5z2wbSMHgZvwT+3zqBjvRJ3SY1BDamjOjuKOPkYdlIAvnC87zPNWAmonAAk w/gaUGvdk9NHFXS64QxMksctDQmN0itoeWHgYmjk6Rg9IHEnIZbJ0MLNmRA6XX5oqSsF afgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BtnIUN6X03hb8vh/PGbquJxO/yPNj/iG0JhEY8dFMbU=; b=hsdMzfvs1fwtc23Od2m1qoowFHbLmhvUYY5mRjwBeJOTu/N68OBQ6HQGCSzo5uLYiy ZrydTJtqTBaWLk8DQlILl2V6ZiPlW1RNnlSSWebl1PmN0tMHkeBW/s7UIy8WIsNDbU4Z QNCvkF6QvA/loks7k3or2x8drX+kC41KpoVGu2MN3cJCFtYuGjmzK0rwArnAkIiSmonU NLps2WiUjuLIEozHsQFHtJUrmmHuR9CJyzujkJFsT0P3ZyvN14VtD8M4DkmEb/xaGAvb 3sYd5PwDdUP9bbRres5XEL6RiIgzYEc7JmEVhVfolvthbkK3DcRHol42y5po2n4a0ShB JdiQ== X-Gm-Message-State: AKwxytdqASG00MMYvE05zm1X1sGE+1ygw+H5uH7KcalyOtntvanE6J0/ O0pFEjgDydRmqprTh7fWgX6q8vcT X-Google-Smtp-Source: ACJfBouOUA0ut8Ca079bx9F2r1ifiQbyomedhdMmMCQ/txBSrEqctIXMY0xlLgAPEsdw7zxXJmd5ZA== X-Received: by 10.98.78.148 with SMTP id c142mr28024961pfb.153.1516248994670; Wed, 17 Jan 2018 20:16:34 -0800 (PST) Received: from chrisp-dl.ws.atlnz.lc ([2001:df5:b000:1::2]) by smtp.gmail.com with ESMTPSA id g8sm8234526pgs.55.2018.01.17.20.16.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 Jan 2018 20:16:34 -0800 (PST) From: Chris Packham To: u-boot@lists.denx.de Date: Thu, 18 Jan 2018 17:16:10 +1300 Message-Id: <20180118041610.20669-5-judge.packham@gmail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180118041610.20669-1-judge.packham@gmail.com> References: <20180118041610.20669-1-judge.packham@gmail.com> Cc: Stefan Roese , Chris Packham Subject: [U-Boot] [PATCH v2 4/4] ddr: marvell: update ddr controller init and freq X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Update the calculation for tWR and tPD. This improves the DDR refresh interval and brings the initialization into line with the binary blobs currently being supplied by Marvell. Signed-off-by: Chris Packham --- Changes in v2: - new drivers/ddr/marvell/a38x/ddr3_topology_def.h | 3 ++- drivers/ddr/marvell/a38x/ddr3_training.c | 33 ++++++++++++++++++---------- drivers/ddr/marvell/a38x/ddr3_training_db.c | 19 +++++++++------- 3 files changed, 34 insertions(+), 21 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_topology_def.h b/drivers/ddr/marvell/a38x/ddr3_topology_def.h index 64a0447dd15b..a17eca041878 100644 --- a/drivers/ddr/marvell/a38x/ddr3_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr3_topology_def.h @@ -70,7 +70,8 @@ enum speed_bin_table_elements { SPEED_BIN_TWTR, SPEED_BIN_TRTP, SPEED_BIN_TWR, - SPEED_BIN_TMOD + SPEED_BIN_TMOD, + SPEED_BIN_TXPDLL }; #endif /* _DDR3_TOPOLOGY_DEF_H */ diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 2eb6e05783d4..ef471e565efd 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -22,6 +22,8 @@ #define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask]) #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num]) +#define TIMES_9_TREFI_CYCLES 0x8 + u32 window_mem_addr = 0; u32 phy_reg0_val = 0; u32 phy_reg1_val = 8; @@ -508,7 +510,9 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("cl_value 0x%x cwl_val 0x%x\n", cl_value, cwl_val)); - + t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index, + SPEED_BIN_TWR), + t_ckclk); data_value = ((cl_mask_table[cl_value] & 0x1) << 2) | ((cl_mask_table[cl_value] & 0xe) << 3); @@ -518,8 +522,9 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ (0x7 << 4) | (1 << 2))); CHECK_STATUS(ddr3_tip_if_write (dev_num, access_type, if_id, - MR0_REG, twr_mask_table[t_wr + 1], - 0xe00)); + MR0_REG, twr_mask_table[t_wr + 1] << 9, + (0x7 << 9))); + /* * MR1: Set RTT and DIC Design GL values @@ -590,16 +595,15 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ DDR_CONTROL_LOW_REG, t2t << 3, 0x3 << 3)); /* move the block to ddr3_tip_set_timing - start */ - t_pd = GET_MAX_VALUE(t_ckclk * 3, - speed_bin_table(speed_bin_index, - SPEED_BIN_TPD)); - t_pd = TIME_2_CLOCK_CYCLES(t_pd, t_ckclk); - txpdll = GET_MAX_VALUE(t_ckclk * 10, 24); + t_pd = TIMES_9_TREFI_CYCLES; + txpdll = GET_MAX_VALUE(t_ckclk * 10, + speed_bin_table(speed_bin_index, + SPEED_BIN_TXPDLL)); txpdll = CEIL_DIVIDE((txpdll - 1), t_ckclk); CHECK_STATUS(ddr3_tip_if_write (dev_num, access_type, if_id, - DDR_TIMING_REG, txpdll << 4, - 0x1f << 4)); + DDR_TIMING_REG, txpdll << 4 | t_pd, + 0x1f << 4 | 0xf)); CHECK_STATUS(ddr3_tip_if_write (dev_num, access_type, if_id, DDR_TIMING_REG, 0x28 << 9, 0x3f << 9)); @@ -1227,6 +1231,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0, bus_cnt = 0, t_hclk = 0, t_wr = 0, refresh_interval_cnt = 0, cnt_id; + u32 t_ckclk; u32 t_refi = 0, end_if, start_if; u32 bus_index = 0; int is_dll_off = 0; @@ -1393,8 +1398,12 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, CHECK_STATUS(ddr3_tip_if_write (dev_num, access_type, if_id, DFS_REG, (cwl_mask_table[cwl_value] << 12), 0x7000)); - t_wr = speed_bin_table(speed_bin_index, SPEED_BIN_TWR); - t_wr = (t_wr / 1000); + + t_ckclk = MEGA / freq_val[frequency]; + t_wr = TIME_2_CLOCK_CYCLES(speed_bin_table(speed_bin_index, + SPEED_BIN_TWR), + t_ckclk); + CHECK_STATUS(ddr3_tip_if_write (dev_num, access_type, if_id, DFS_REG, (twr_mask_table[t_wr + 1] << 16), 0x70000)); diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c index 861dfb19c366..0e11b434ab67 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c @@ -152,18 +152,18 @@ u8 twr_mask_table[] = { 10, 10, 10, - 1, /*5 */ - 2, /*6 */ - 3, /*7 */ + 1, /*5*/ + 2, /*6*/ + 3, /*7*/ + 4, /*8*/ 10, + 5, /*10*/ 10, - 5, /*10 */ + 6, /*12*/ 10, - 6, /*12 */ + 7, /*14*/ 10, - 7, /*14 */ - 10, - 0 /*16 */ + 0 /*16*/ }; u8 cl_mask_table[] = { @@ -431,6 +431,9 @@ u32 speed_bin_table(u8 index, enum speed_bin_table_elements element) case SPEED_BIN_TMOD: result = 15000; break; + case SPEED_BIN_TXPDLL: + result = 24000; + break; default: break; }