From patchwork Wed Jan 17 13:56:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 862276 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vanguardiasur-com-ar.20150623.gappssmtp.com header.i=@vanguardiasur-com-ar.20150623.gappssmtp.com header.b="lY1zLriR"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zM7w40Y4kz9sNc for ; Thu, 18 Jan 2018 00:58:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2A75DC21E18; Wed, 17 Jan 2018 13:57:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DA33FC21E0E; Wed, 17 Jan 2018 13:57:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EE4D5C21DFA; Wed, 17 Jan 2018 13:56:55 +0000 (UTC) Received: from mail-qt0-f193.google.com (mail-qt0-f193.google.com [209.85.216.193]) by lists.denx.de (Postfix) with ESMTPS id DF50AC21E2F for ; Wed, 17 Jan 2018 13:56:51 +0000 (UTC) Received: by mail-qt0-f193.google.com with SMTP id d4so22597963qtj.5 for ; Wed, 17 Jan 2018 05:56:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HkbnaiTN7HX5icyqgpRbo2q1W1niXCJaWg2WAzHsQ1I=; b=lY1zLriRygvqnK/Y8ds/UHE55gwiI/zL2L2+d1u0O5WFv2Rt7smMYIwyOHUyY1fsuI 2g9LxE1oCTVqhh4/doMcwaMZbKGDh/b+KpLmhO/VPkBL+Twr0PH2n4ZY1hDXc5AGyZbV 2hDYXKceH2yCLW3FTnKws72o6olfWM+1Zq60yiZvcvEJd6xdvmxBeMtzufnWAhquMXrk c6R4cSl2saaQOOfTRSUf0xieoPXvbi85RiwZS3ilV2PG4Rtc/5jLoH/NfYSsUeDkczJE VJpJ1dwdVfYZ/KPp4FhXyfGjO2Fd3qMQYiVKbcR5ljdH7I9MKhgtOBeuu4Lf2aFnE1Ma jy1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HkbnaiTN7HX5icyqgpRbo2q1W1niXCJaWg2WAzHsQ1I=; b=XGefXT6pwC0+k3CJaGJy1aJ2iGODBIQoYwEzRqfcz4riUoGWJ36WX1/gulHegFtoRP hJiEAdnzuNNHxBfKljC8TxS+YgJqb3m07m/h5KWEd3krTcdyPckqSZ0SDBXYkSSj8kUC CkJWzgtHaG/uukxvMHy04BV2AtHmyL1ub15isdD6c/UFicKgWzxn4XDGjBWbfO67WylS PDuAyHyPIcKNuM0yJFrZ2aGmj2xun4iDpcxHFDkCbYvAbYdDQ7iJ0XOs9izzSD2XOg5Z 78Tk8YgGO8sN8GVl1IG4F4EEXOpkL8HXQ3Cu0OjQUc7S/F8V2buZREbAM2o9GMsr2xGA dm+A== X-Gm-Message-State: AKwxytetwl/NYK22tSak4xlmLJnfMj3AfKwYupbSZJCqni3WT0gxJzws nQOMJoSZBtvkIP7IZjPPKpg0mFn1 X-Google-Smtp-Source: ACJfBot+q/CJ2KAYiUM85R9nchbW90EHiK/GOry/AyCELLSNkBfEQN5FI8KYYrSt2l+Ekk5XHrC/og== X-Received: by 10.200.27.91 with SMTP id p27mr26056918qtk.254.1516197410549; Wed, 17 Jan 2018 05:56:50 -0800 (PST) Received: from ezelaptop.fibertel.com.ar ([190.210.56.45]) by smtp.gmail.com with ESMTPSA id r2sm2871366qkb.54.2018.01.17.05.56.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Jan 2018 05:56:49 -0800 (PST) From: Ezequiel Garcia To: u-boot@lists.denx.de Date: Wed, 17 Jan 2018 10:56:23 -0300 Message-Id: <20180117135626.22498-3-ezequiel@vanguardiasur.com.ar> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180117135626.22498-1-ezequiel@vanguardiasur.com.ar> References: <20180117135626.22498-1-ezequiel@vanguardiasur.com.ar> Cc: michal.simek@xilinx.com Subject: [U-Boot] [PATCH 2/5] zynq: Rework FPGA initialization X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit moves the FPGA descriptor definition to mach-zynq, where it makes more sense. Also, the implementation is reworked to be cleaner and a bit smaller. add/remove: 2/11 grow/shrink: 0/1 up/down: 420/-608 (-188) function old new delta zynq_fpga_descs - 352 +352 zynq_fpga_desc - 68 +68 fpga100 28 - -28 fpga045 28 - -28 fpga035 28 - -28 fpga030 28 - -28 fpga020 28 - -28 fpga015 28 - -28 fpga014s 28 - -28 fpga012s 28 - -28 fpga010 28 - -28 fpga007s 28 - -28 fpga 28 - -28 board_init 332 32 -300 Total: Before=574182, After=573994, chg -0.03% Signed-off-by: Ariel D'Alessandro Signed-off-by: Ezequiel Garcia --- arch/arm/mach-zynq/cpu.c | 41 +++++++++++++++++++- arch/arm/mach-zynq/include/mach/sys_proto.h | 3 ++ board/xilinx/zynq/board.c | 59 +---------------------------- 3 files changed, 44 insertions(+), 59 deletions(-) diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index ee1c1a943b66..53a07b0059c2 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -5,14 +5,36 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include -#include #include +#include +#include #define ZYNQ_SILICON_VER_MASK 0xF0000000 #define ZYNQ_SILICON_VER_SHIFT 28 +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static const struct { + u8 idcode; + xilinx_desc desc; +} zynq_fpga_descs[] = { + { .idcode = XILINX_ZYNQ_7007S, .desc = XILINX_XC7Z007S_DESC(0x07) }, + { .idcode = XILINX_ZYNQ_7010, .desc = XILINX_XC7Z010_DESC(0x10) }, + { .idcode = XILINX_ZYNQ_7012S, .desc = XILINX_XC7Z012S_DESC(0x12) }, + { .idcode = XILINX_ZYNQ_7014S, .desc = XILINX_XC7Z014S_DESC(0x14) }, + { .idcode = XILINX_ZYNQ_7015, .desc = XILINX_XC7Z015_DESC(0x15) }, + { .idcode = XILINX_ZYNQ_7020, .desc = XILINX_XC7Z020_DESC(0x20) }, + { .idcode = XILINX_ZYNQ_7030, .desc = XILINX_XC7Z030_DESC(0x30) }, + { .idcode = XILINX_ZYNQ_7035, .desc = XILINX_XC7Z035_DESC(0x35) }, + { .idcode = XILINX_ZYNQ_7045, .desc = XILINX_XC7Z045_DESC(0x45) }, + { .idcode = XILINX_ZYNQ_7100, .desc = XILINX_XC7Z100_DESC(0x100) }, + { /* Sentinel */ }, +}; +#endif + int arch_cpu_init(void) { zynq_slcr_unlock(); @@ -60,3 +82,20 @@ void enable_caches(void) dcache_enable(); } #endif + +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +const xilinx_desc *zynq_fpga_desc(void) +{ + u32 idcode; + u8 i; + + idcode = zynq_slcr_get_idcode(); + for (i = 0; zynq_fpga_descs[i].idcode; i++) { + if (zynq_fpga_descs[i].idcode == idcode) { + return &zynq_fpga_descs[i].desc; + } + } + return NULL; +} +#endif diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h index af61352dd110..fd5744c4e85e 100644 --- a/arch/arm/mach-zynq/include/mach/sys_proto.h +++ b/arch/arm/mach-zynq/include/mach/sys_proto.h @@ -7,6 +7,8 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +#include + extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); @@ -16,6 +18,7 @@ extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); +extern const xilinx_desc *zynq_fpga_desc(void); extern unsigned int zynq_get_silicon_version(void); int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index e59038106aa6..f9e7bca4ee40 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -15,69 +15,12 @@ DECLARE_GLOBAL_DATA_PTR; -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) -static xilinx_desc fpga; - -/* It can be done differently */ -static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); -static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); -static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); -static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); -static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); -static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); -static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); -#endif - int board_init(void) { -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) - u32 idcode; - - idcode = zynq_slcr_get_idcode(); - - switch (idcode) { - case XILINX_ZYNQ_7007S: - fpga = fpga007s; - break; - case XILINX_ZYNQ_7010: - fpga = fpga010; - break; - case XILINX_ZYNQ_7012S: - fpga = fpga012s; - break; - case XILINX_ZYNQ_7014S: - fpga = fpga014s; - break; - case XILINX_ZYNQ_7015: - fpga = fpga015; - break; - case XILINX_ZYNQ_7020: - fpga = fpga020; - break; - case XILINX_ZYNQ_7030: - fpga = fpga030; - break; - case XILINX_ZYNQ_7035: - fpga = fpga035; - break; - case XILINX_ZYNQ_7045: - fpga = fpga045; - break; - case XILINX_ZYNQ_7100: - fpga = fpga100; - break; - } -#endif - #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) fpga_init(); - fpga_add(fpga_xilinx, &fpga); + fpga_add(fpga_xilinx, (void *)zynq_fpga_desc()); #endif return 0;