From patchwork Wed Jan 17 13:56:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 862277 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vanguardiasur-com-ar.20150623.gappssmtp.com header.i=@vanguardiasur-com-ar.20150623.gappssmtp.com header.b="K2hMFnkH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zM7w71YWtz9sNx for ; Thu, 18 Jan 2018 00:58:14 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A6753C21E28; Wed, 17 Jan 2018 13:57:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 66FDAC21E0E; Wed, 17 Jan 2018 13:57:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 39888C21E0E; Wed, 17 Jan 2018 13:56:52 +0000 (UTC) Received: from mail-qt0-f194.google.com (mail-qt0-f194.google.com [209.85.216.194]) by lists.denx.de (Postfix) with ESMTPS id 609D6C21C3F for ; Wed, 17 Jan 2018 13:56:49 +0000 (UTC) Received: by mail-qt0-f194.google.com with SMTP id m59so22594680qte.11 for ; Wed, 17 Jan 2018 05:56:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/+2PMO5vEOT/fQVNN/abVp7C4EELATS1ZyJlRVQRDeQ=; b=K2hMFnkHrnebIxj9zmeelDIDkk8qhta/jGVslV18hEwMTxLYfCMw1fH1WJgS6lz4oF yUb7Wn9R9qQVnDBfbbG3JkSvuG7BES8ILnD6E5eQcLa1+CDWfAJX8or1ALWafWMu9K38 K2kbGGlCB7QONXbfbQfKmRZv99al3tD1607ZdVrvndX0frUl2zzoMEgXCkgYxJXMJ6rd dl6IYVkJ6Lfxq1s+zvloUfvHl9BS4nfbX4zeTrnqu31PpEHCogdkNyW/pr0W4mbWz1JN gZfkvQFgrlj9MapGEZfaVhmLQW/TBu+ZpF5QQs5mE7T5rbvY2WGxrhaP3OLkcgNiSJVF pixg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/+2PMO5vEOT/fQVNN/abVp7C4EELATS1ZyJlRVQRDeQ=; b=QktW5F54nTT667pSGvAFPq2cxMw/2MJDYwDDcZpQtyYI2oD0mlpp8LmJqGVpt9taI5 mMVGHTWAqJapkxggoGwu73Kq7AGguvE+zrZmvsBJ1+EtpX2R1rmSDwooqAKtWD1qAoW8 ALDlHTyJSzCiNryFyrf43Zst0UedmjkKDKOuyuQiT6dYw/3TqR/1UpxdOt+kNmGC+QiZ w9waFGWXvTx8aUqF2GVjPur2TATsAlWpuG8rvf+ewhhObs1g9zZzTHrNpBVeiLFeyE6t nbpSJ8aYTwMXUN2g7lG+4r80UVWN27pqgg+qLn6AM7g99fE6h/uneh6CkVbp4GZ3e0DA kErg== X-Gm-Message-State: AKwxytfRDu7jKMXPAxy3QerbwDngog4uHXLn/EtyahdNuLkqFQl85whG 151Byu03+IfxC+l8b1lajzqJbiK6 X-Google-Smtp-Source: ACJfBou0DcKx17L2UY+LttYCaVrNCvBm3icrvRYnJL/8YiiJLg00bOcdp3dYLgfVYKBLSyJHBiwOXQ== X-Received: by 10.237.41.225 with SMTP id o88mr21466350qtd.184.1516197408142; Wed, 17 Jan 2018 05:56:48 -0800 (PST) Received: from ezelaptop.fibertel.com.ar ([190.210.56.45]) by smtp.gmail.com with ESMTPSA id r2sm2871366qkb.54.2018.01.17.05.56.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Jan 2018 05:56:47 -0800 (PST) From: Ezequiel Garcia To: u-boot@lists.denx.de Date: Wed, 17 Jan 2018 10:56:22 -0300 Message-Id: <20180117135626.22498-2-ezequiel@vanguardiasur.com.ar> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180117135626.22498-1-ezequiel@vanguardiasur.com.ar> References: <20180117135626.22498-1-ezequiel@vanguardiasur.com.ar> Cc: michal.simek@xilinx.com Subject: [U-Boot] [PATCH 1/5] zynq: Define macros for the device names X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This will allow to reuse the macros when showing the CPU info. Signed-off-by: Ezequiel Garcia --- include/zynqpl.h | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/include/zynqpl.h b/include/zynqpl.h index 5a34a17daefe..e10a266643bd 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -42,45 +42,57 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_XC7Z045_SIZE 106571232/8 #define XILINX_XC7Z100_SIZE 139330784/8 +/* Device Names */ +#define XILINX_XC7Z007S_NAME "7z007s" +#define XILINX_XC7Z010_NAME "7z010" +#define XILINX_XC7Z012S_NAME "7z012s" +#define XILINX_XC7Z014S_NAME "7z014s" +#define XILINX_XC7Z015_NAME "7z015" +#define XILINX_XC7Z020_NAME "7z020" +#define XILINX_XC7Z030_NAME "7z030" +#define XILINX_XC7Z035_NAME "7z035" +#define XILINX_XC7Z045_NAME "7z045" +#define XILINX_XC7Z100_NAME "7z100" + /* Descriptor Macros */ #define XILINX_XC7Z007S_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z007s" } + XILINX_XC7Z007S_NAME } #define XILINX_XC7Z010_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z010" } + XILINX_XC7Z010_NAME } #define XILINX_XC7Z012S_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z012s" } + XILINX_XC7Z012S_NAME } #define XILINX_XC7Z014S_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z014s" } + XILINX_XC7Z014S_NAME } #define XILINX_XC7Z015_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z015" } + XILINX_XC7Z015_NAME } #define XILINX_XC7Z020_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z020" } + XILINX_XC7Z020_NAME } #define XILINX_XC7Z030_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z030" } + XILINX_XC7Z030_NAME } #define XILINX_XC7Z035_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z035" } + XILINX_XC7Z035_NAME } #define XILINX_XC7Z045_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z045" } + XILINX_XC7Z045_NAME } #define XILINX_XC7Z100_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z100" } + XILINX_XC7Z100_NAME } #endif /* _ZYNQPL_H_ */