diff mbox series

[U-Boot,1/5] zynq: Define macros for the device names

Message ID 20180117135626.22498-2-ezequiel@vanguardiasur.com.ar
State Superseded
Delegated to: Michal Simek
Headers show
Series zynq: Fun with board and CPU info display | expand

Commit Message

Ezequiel Garcia Jan. 17, 2018, 1:56 p.m. UTC 
This will allow to reuse the macros when showing
the CPU info.

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
---
 include/zynqpl.h | 32 ++++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/include/zynqpl.h b/include/zynqpl.h
index 5a34a17daefe..e10a266643bd 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -42,45 +42,57 @@  extern struct xilinx_fpga_op zynq_op;
 #define XILINX_XC7Z045_SIZE	106571232/8
 #define XILINX_XC7Z100_SIZE	139330784/8
 
+/* Device Names */
+#define XILINX_XC7Z007S_NAME	"7z007s"
+#define XILINX_XC7Z010_NAME	"7z010"
+#define XILINX_XC7Z012S_NAME	"7z012s"
+#define XILINX_XC7Z014S_NAME	"7z014s"
+#define XILINX_XC7Z015_NAME	"7z015"
+#define XILINX_XC7Z020_NAME	"7z020"
+#define XILINX_XC7Z030_NAME	"7z030"
+#define XILINX_XC7Z035_NAME	"7z035"
+#define XILINX_XC7Z045_NAME	"7z045"
+#define XILINX_XC7Z100_NAME	"7z100"
+
 /* Descriptor Macros */
 #define XILINX_XC7Z007S_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z007s" }
+	XILINX_XC7Z007S_NAME }
 
 #define XILINX_XC7Z010_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z010" }
+	XILINX_XC7Z010_NAME }
 
 #define XILINX_XC7Z012S_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z012s" }
+	XILINX_XC7Z012S_NAME }
 
 #define XILINX_XC7Z014S_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z014s" }
+	XILINX_XC7Z014S_NAME }
 
 #define XILINX_XC7Z015_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z015" }
+	XILINX_XC7Z015_NAME }
 
 #define XILINX_XC7Z020_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z020" }
+	XILINX_XC7Z020_NAME }
 
 #define XILINX_XC7Z030_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z030" }
+	XILINX_XC7Z030_NAME }
 
 #define XILINX_XC7Z035_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z035" }
+	XILINX_XC7Z035_NAME }
 
 #define XILINX_XC7Z045_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z045" }
+	XILINX_XC7Z045_NAME }
 
 #define XILINX_XC7Z100_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
-	"7z100" }
+	XILINX_XC7Z100_NAME }
 
 #endif /* _ZYNQPL_H_ */