| Message ID | 20170904053832.12229-2-judge.packham@gmail.com |
|---|---|
| State | Accepted |
| Commit | 631407c5c03b8503b7f297452154d6100d95510b |
| Headers | show |
| Series | [U-Boot,next,v2,1/2] ARM: mvebu: Add SoC IDs for Marvell's integrated CPUs | expand |
On 04.09.2017 07:38, Chris Packham wrote: > From: Joshua Scott <joshua.scott@alliedtelesis.co.nz> > > Display more information about the current RAM configuration. With these > changes the output on a 88F6820 board is > > SoC: MV88F6820-A0 at 1600 MHz > DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled) > > Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> > Signed-off-by: Chris Packham <judge.packham@gmail.com> > --- > One of the hardware designers at $dayjob expressed a desire to keep > track of various tweaks to the DDR setup during hardware debugging > sessions. This is the result. > > I've based this on what is available for the fsl platforms. It might be > nice to add a few more things but I'm concious of keeping the > information relevant and succinct. > > Changes in v2: > - A375 and A38x have 16/32b DDR bus > > arch/arm/mach-mvebu/dram.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan
On 04.09.2017 07:38, Chris Packham wrote: > From: Joshua Scott <joshua.scott@alliedtelesis.co.nz> > > Display more information about the current RAM configuration. With these > changes the output on a 88F6820 board is > > SoC: MV88F6820-A0 at 1600 MHz > DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled) > > Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> > Signed-off-by: Chris Packham <judge.packham@gmail.com> > --- > One of the hardware designers at $dayjob expressed a desire to keep > track of various tweaks to the DDR setup during hardware debugging > sessions. This is the result. > > I've based this on what is available for the fsl platforms. It might be > nice to add a few more things but I'm concious of keeping the > information relevant and succinct. > > Changes in v2: > - A375 and A38x have 16/32b DDR bus Applied to u-boot-marvell/master. Thanks, Stefan
diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index e3f304c36683..55e9ad726a88 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -216,6 +216,35 @@ static int ecc_enabled(void) return 0; } + +/* Return the width of the DRAM bus, or 0 for unknown. */ +static int bus_width(void) +{ + int full_width = 0; + + if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS)) + full_width = 1; + + switch (mvebu_soc_family()) { + case MVEBU_SOC_AXP: + return full_width ? 64 : 32; + break; + case MVEBU_SOC_A375: + case MVEBU_SOC_A38X: + case MVEBU_SOC_MSYS: + return full_width ? 32 : 16; + default: + return 0; + } +} + +static int cycle_mode(void) +{ + int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR); + + return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK; +} + #else static void dram_ecc_scrubbing(void) { @@ -295,10 +324,26 @@ int dram_init_banksize(void) void board_add_ram_info(int use_default) { struct sar_freq_modes sar_freq; + int mode; + int width; get_sar_freq(&sar_freq); printf(" (%d MHz, ", sar_freq.d_clk); + width = bus_width(); + if (width) + printf("%d-bit, ", width); + + mode = cycle_mode(); + /* Mode 0 = Single cycle + * Mode 1 = Two cycles (2T) + * Mode 2 = Three cycles (3T) + */ + if (mode == 1) + printf("2T, "); + if (mode == 2) + printf("3T, "); + if (ecc_enabled()) printf("ECC"); else