From patchwork Mon Aug 28 12:16:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 806554 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xgrNj28W6z9sMN for ; Mon, 28 Aug 2017 22:16:53 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E8E5CC21DAB; Mon, 28 Aug 2017 12:16:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3D594C21DA4; Mon, 28 Aug 2017 12:16:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 22192C21DA4; Mon, 28 Aug 2017 12:16:41 +0000 (UTC) Received: from mail.free-electrons.com (mail.free-electrons.com [62.4.15.54]) by lists.denx.de (Postfix) with ESMTP id CF47CC21C54 for ; Mon, 28 Aug 2017 12:16:40 +0000 (UTC) Received: by mail.free-electrons.com (Postfix, from userid 110) id 9334320A31; Mon, 28 Aug 2017 14:16:39 +0200 (CEST) Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 6B6102096D; Mon, 28 Aug 2017 14:16:39 +0200 (CEST) From: Thomas Petazzoni To: Hiroyuki Yokoyama , Nobuhiro Iwamatsu , Vladimir Zapolskiy , u-boot@lists.denx.de Date: Mon, 28 Aug 2017 14:16:38 +0200 Message-Id: <20170828121638.13751-1-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.9.4 Cc: Thomas Petazzoni Subject: [U-Boot] [PATCH] serial: serial_sh: take into account port->clk_mode for SH7785/7786 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a, which means bits CKE1/CKE0 have the value 10b. This tells the SCIF that the "External clock/SCIF_SCK pin functions as clock input". However, this is not the case in all designs, and it's the purpose of the clk_mode = EXT_CLK to indicate such a setting. In order for the serial_sh driver to work on a SH7786 platform that does not use SCIF_SCK as a clock input, we have to adjust the SCSCR_INIT value, to have CKE1/CKE0 set to 00b. This is similar to what is done for other SH platforms. Signed-off-by: Thomas Petazzoni --- drivers/serial/serial_sh.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 4d27122..d7bbd1a 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -184,7 +184,8 @@ struct uart_port { # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ -# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x3a : 0x38) + /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_CPU_SH7201) || \ defined(CONFIG_CPU_SH7203) || \ defined(CONFIG_CPU_SH7206) || \