From patchwork Wed Jul 12 14:48:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 787306 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3x722G4yksz9s74 for ; Thu, 13 Jul 2017 00:51:02 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6F1EBC21D8D; Wed, 12 Jul 2017 14:50:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 49BF9C21D8D; Wed, 12 Jul 2017 14:50:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1B295C21C38; Wed, 12 Jul 2017 14:50:03 +0000 (UTC) Received: from mail.free-electrons.com (mail.free-electrons.com [62.4.15.54]) by lists.denx.de (Postfix) with ESMTP id A8AA1C21C2B for ; Wed, 12 Jul 2017 14:50:02 +0000 (UTC) Received: by mail.free-electrons.com (Postfix, from userid 110) id C7DEE21FBE; Wed, 12 Jul 2017 16:50:00 +0200 (CEST) Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 9EDE42087B; Wed, 12 Jul 2017 16:50:00 +0200 (CEST) From: Maxime Ripard To: Jagan Teki , Jaehoon Chung Date: Wed, 12 Jul 2017 16:48:37 +0200 Message-Id: <20170712144838.15608-1-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.13.0 Cc: u-boot@lists.denx.de, Maxime Ripard Subject: [U-Boot] [PATCH 1/2] mmc: sunxi: Support the new mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Almost all of the newer Allwinner SoCs have a new operating mode for the eMMC clocks that needs to be enabled in both the clock and the MMC controller. Add support for it through a Kconfig option Signed-off-by: Maxime Ripard --- arch/arm/include/asm/arch-sunxi/mmc.h | 9 ++++++--- drivers/mmc/Kconfig | 3 +++ drivers/mmc/sunxi_mmc.c | 26 +++++++++++++++++++++++--- 3 files changed, 32 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index cb52e648731c..0c2d496295ff 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -35,16 +35,19 @@ struct sunxi_mmc { u32 cbcr; /* 0x48 CIU byte count */ u32 bbcr; /* 0x4c BIU byte count */ u32 dbgc; /* 0x50 debug enable */ - u32 res0[11]; + u32 res0; /* 0x54 reserved */ + u32 a12a; /* 0x58 Auto command 12 argument */ + u32 ntsr; /* 0x5c New timing set register */ + u32 res1[8]; u32 dmac; /* 0x80 internal DMA control */ u32 dlba; /* 0x84 internal DMA descr list base address */ u32 idst; /* 0x88 internal DMA status */ u32 idie; /* 0x8c internal DMA interrupt enable */ u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ - u32 res1[26]; + u32 res2[26]; #ifdef CONFIG_SUNXI_GEN_SUN6I - u32 res2[64]; + u32 res3[64]; #endif u32 fifo; /* 0x100 / 0x200 FIFO access address */ }; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 82b8d756867c..203f59547100 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -368,6 +368,9 @@ config MMC_SUNXI This selects support for the SD/MMC Host Controller on Allwinner sunxi SoCs. +config MMC_SUNXI_HAS_NEW_MODE + bool + config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91 diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index fd3fc2af40a0..68750f3832b6 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -87,6 +87,20 @@ static int mmc_resource_init(int sdc_no) static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) { unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; + bool new_mode = false; + u32 val = 0; + +#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE + if (mmchost->mmc_no == 2) + new_mode = true; +#endif + + /* + * The MMC clock has an extra /2 post-divider when operating in the new + * mode. + */ + if (new_mode) + hz = hz * 2; if (hz <= 24000000) { pll = CCM_MMC_CTRL_OSCM24; @@ -143,9 +157,15 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) #endif } - writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | - CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | - CCM_MMC_CTRL_M(div), mmchost->mclkreg); + if (new_mode) { + val = BIT(30); + writel(BIT(31), &mmchost->reg->ntsr); + } else { + val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | CCM_MMC_CTRL_SCLK_DLY(sclk_dly); + } + + writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_M(div) | val, + mmchost->mclkreg); debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", mmchost->mmc_no, hz, pll_hz, 1u << n, div,