From patchwork Tue Apr 18 02:20:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 751657 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3w6Z81221Wz9s2G for ; Tue, 18 Apr 2017 15:54:09 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 06B45C21C49; Tue, 18 Apr 2017 05:51:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 64989C21C99; Tue, 18 Apr 2017 05:49:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9C46EC21C98; Tue, 18 Apr 2017 05:49:12 +0000 (UTC) Received: from wens.csie.org (mirror2.csie.ntu.edu.tw [140.112.30.76]) by lists.denx.de (Postfix) with ESMTPS id 810CAC21C33 for ; Tue, 18 Apr 2017 05:49:07 +0000 (UTC) Received: by wens.csie.org (Postfix, from userid 1000) id 2ECE45FD3F; Tue, 18 Apr 2017 10:20:44 +0800 (CST) From: Chen-Yu Tsai To: u-boot@lists.denx.de Date: Tue, 18 Apr 2017 10:20:21 +0800 Message-Id: <20170418022029.23894-6-wens@csie.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170418022029.23894-1-wens@csie.org> References: <20170418022029.23894-1-wens@csie.org> Cc: Jagan Teki , linux-sunxi@googlegroups.com, Maxime Ripard Subject: [U-Boot] [PATCH resend v2 05/13] sunxi: Add mmc[1-3] pinmux settings for R40 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The PIO is generally compatible with the A20, except that it routes the full 8 bits and eMMC reset pins for mmc2. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard --- board/sunxi/board.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 495cb591a9fb..21ce8348922c 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -199,7 +199,8 @@ static void mmc_pinmux_setup(int sdc) case 1: pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) if (pins == SUNXI_GPIO_H) { /* SDC1: PH22-PH-27 */ for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { @@ -294,6 +295,17 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(SUNXI_GPC(24), 2); } +#elif defined(CONFIG_MACH_SUN8I_R40) + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) /* SDC2: PC5-PC6, PC8-PC16 */ for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { @@ -320,7 +332,8 @@ static void mmc_pinmux_setup(int sdc) case 3: pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) /* SDC3: PI4-PI9 */ for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);