diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2554a2cd14..3421f273b5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1046,6 +1046,7 @@ source "board/freescale/mx53loco/Kconfig"
 source "board/freescale/mx53smd/Kconfig"
 source "board/freescale/s32v234evb/Kconfig"
 source "board/freescale/vf610twr/Kconfig"
+source "board/grinn/chiliboard/Kconfig"
 source "board/gumstix/pepper/Kconfig"
 source "board/h2200/Kconfig"
 source "board/hisilicon/hikey/Kconfig"
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index b1a0f0f356..57e1a93211 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -59,6 +59,12 @@ config TARGET_BAV335X
 
 	  For more information, visit: http://birdland.com/oem
 
+config TARGET_CHILIBOARD
+	bool "Grinn chiliBoard"
+	select AM33XX_CHILISOM
+	select DM
+	select DM_SERIAL
+
 config TARGET_CM_T335
 	bool "Support cm_t335"
 	select DM
diff --git a/board/grinn/chiliboard/Kconfig b/board/grinn/chiliboard/Kconfig
new file mode 100644
index 0000000000..20056e81a1
--- /dev/null
+++ b/board/grinn/chiliboard/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CHILIBOARD
+
+config SYS_BOARD
+	default "chiliboard"
+
+config SYS_VENDOR
+	default "grinn"
+
+config SYS_CONFIG_NAME
+	default "chiliboard"
+
+config SYS_SOC
+	default "am33xx"
+
+endif
diff --git a/board/grinn/chiliboard/MAINTAINERS b/board/grinn/chiliboard/MAINTAINERS
new file mode 100644
index 0000000000..5eaccb2791
--- /dev/null
+++ b/board/grinn/chiliboard/MAINTAINERS
@@ -0,0 +1,8 @@
+CHILIBOARD
+M:	Marcin Niestroj <m.niestroj@grinn-global.com>
+S:	Maintained
+F:	arch/arm/include/asm/arch-am33xx/chilisom.h
+F:	arch/arm/mach-omap2/am33xx/chilisom.c
+F:	board/grinn/chiliboard/
+F:	include/configs/chiliboard.h
+F:	configs/chiliboard_defconfig
diff --git a/board/grinn/chiliboard/Makefile b/board/grinn/chiliboard/Makefile
new file mode 100644
index 0000000000..865968d1a7
--- /dev/null
+++ b/board/grinn/chiliboard/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2017 Grinn
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := board.o
diff --git a/board/grinn/chiliboard/README b/board/grinn/chiliboard/README
new file mode 100644
index 0000000000..cea4c1d42e
--- /dev/null
+++ b/board/grinn/chiliboard/README
@@ -0,0 +1,31 @@
+How to use U-Boot on Grinn's chiliBoard
+--------------------------------------
+
+- Build U-Boot for chiliBoard:
+
+$ make mrproper
+$ make chiliboard_defconfig
+$ make
+
+This will generate the SPL image called MLO and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=MLO of=/dev/mmcblk0 bs=128k; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=128k seek=3; sync
+
+- Jumper settings:
+
+S2: 1 1 1 0 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Insert the micro SD card in the board.
+
+- Connect USB cable between chiliBoard and the PC for the power and console.
+
+- U-Boot messages should come up.
diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
new file mode 100644
index 0000000000..e3f82b0a80
--- /dev/null
+++ b/board/grinn/chiliboard/board.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2017, Grinn - http://grinn-global.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/chilisom.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <asm/io.h>
+#include <cpsw.h>
+#include <environment.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <serial.h>
+#include <spl.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static __maybe_unused struct ctrl_dev *cdev =
+	(struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REFCLK */
+	{-1},
+};
+
+static void enable_board_pin_mux(void)
+{
+	chilisom_enable_pin_mux();
+
+	/* chiliboard pinmux */
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+}
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifndef CONFIG_DM_SERIAL
+struct serial_device *default_serial_console(void)
+{
+	return &eserial1_device;
+}
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+void set_uart_mux_conf(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+void am33xx_spl_board_init(void)
+{
+	chilisom_spl_board_init();
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+#endif
+
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW) && \
+	!defined(CONFIG_SPL_BUILD)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	}
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+
+	writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+
+	return n;
+}
+#endif
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
new file mode 100644
index 0000000000..4e94214204
--- /dev/null
+++ b/configs/chiliboard_defconfig
@@ -0,0 +1,45 @@
+CONFIG_ARM=y
+CONFIG_AM33XX=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TARGET_CHILIBOARD=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_GPIO=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
new file mode 100644
index 0000000000..04ee3a1d3c
--- /dev/null
+++ b/include/configs/chiliboard.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2017 Grinn - http://grinn-global.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CHILIBOARD_H
+#define __CONFIG_CHILIBOARD_H
+
+#define CONFIG_NAND
+
+#include <configs/ti_am335x_common.h>
+
+#define CONFIG_CONS_INDEX		1
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+#endif
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} ${optargs} " \
+		"${mtdparts} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdt_addr} NAND.u-boot-spl-os; " \
+		"nand read ${loadaddr} NAND.kernel; " \
+		"bootz ${loadaddr} - ${fdt_addr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot; " \
+	"run nandboot; " \
+	"run netboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"fdt_addr=0x87800000\0" \
+	"boot_fdt=try\0" \
+	"console=ttyO0,115200n8\0" \
+	"image=zImage\0" \
+	"fdt_file=am335x-chiliboard.dtb\0" \
+	"ip_dyn=yes\0" \
+	"optargs=\0" \
+	"loadbootscript=" \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${boot_dir}/${image}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
+		"${boot_dir}/${fdt_file}\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} ${optargs} " \
+		"${mtdparts} " \
+		"root=${mmcroot}\0" \
+	"mmcloados=run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadimage; then " \
+				"run mmcloados;" \
+			"fi;" \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} ${optargs} " \
+		"${mtdparts} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	NANDARGS
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+#define CONFIG_BAUDRATE			115200
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+
+/* SPL */
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
+
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_GPMC_PREFETCH
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define MTDIDS_DEFAULT			"nand0=8000000.nand"
+#define MTDPARTS_DEFAULT		"mtdparts=8000000.nand:" \
+					"128k(NAND.SPL)," \
+					"128k(NAND.SPL.backup1)," \
+					"128k(NAND.SPL.backup2)," \
+					"128k(NAND.SPL.backup3)," \
+					"256k(NAND.u-boot-spl-os)," \
+					"1m(NAND.u-boot)," \
+					"128k(NAND.u-boot-env)," \
+					"128k(NAND.u-boot-env.backup1)," \
+					"8m(NAND.kernel)," \
+					"-(NAND.file-system)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#undef CONFIG_DM_USB
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET		0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#define CONFIG_ENV_SIZE			SZ_128K
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#else
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		SZ_128K
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* Network. */
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#endif	/* ! __CONFIG_CHILIBOARD_H */
