From patchwork Wed Oct 26 01:26:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 686842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3t3XTG1vfRz9t0J for ; Wed, 26 Oct 2016 12:28:02 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=gj7N9d6u; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ACD6DA75B8; Wed, 26 Oct 2016 03:27:22 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id np_SbMQvK3tp; Wed, 26 Oct 2016 03:27:22 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D4CEBA7615; Wed, 26 Oct 2016 03:27:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EE6BEA7534 for ; Wed, 26 Oct 2016 03:27:07 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YIcaAcoLZ9A2 for ; Wed, 26 Oct 2016 03:27:07 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by theia.denx.de (Postfix) with ESMTPS id 0F73AA75C6 for ; Wed, 26 Oct 2016 03:26:51 +0200 (CEST) Received: by mail-pf0-f194.google.com with SMTP id i85so21076066pfa.0 for ; Tue, 25 Oct 2016 18:26:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QBEEk1q8KhsNHYz5j2Q4YC0sKl/pXrgXeav35AM2UhY=; b=gj7N9d6uvLdg1j50MNhaLKaAfpkWs7HDQpXmDnu/LyGxCSKS+nrEIud/uz/bBdEHxB Lfiq3lQ5qJCbgMQuTHierALI9zXxxAxjaTVTCeiUfYiAfx39wpg0i7LumkAgB6mALw8v RSwRBJ+fQutdJjzucFQpQNARIsIe6Cm0TEkkz519r69s8yNqOc/0GPfaDz6FyFaCLdc+ 9uqzsdu6OFiT+opsLlaUk4lFkz255nOiFj5C7/pfbXyYcaEbyAVFw5O2dojrOZrInUxz rgPCq1JejHME9K6lokHMErub2Y+VpCYsI2i3LQJD+WEiW2gMHO5+FPa9f2rKWL8pv49F ONWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QBEEk1q8KhsNHYz5j2Q4YC0sKl/pXrgXeav35AM2UhY=; b=QBa47VJaS4yqzkxB9pHdIA79u8p6L55Ezlw8zX0eDnfshSTLFgyVr1bmXF8zxwCESf gb8W+MZEwWPhFPSDBrHKKFgvzngepD/363lkDs9o/ofcvPVDE01IIaBC7zje1c/VQwwZ bnPys1gzhwQ7EmgLPAdQ4CTiRszaB3YdNV26suHWCp45Yd5HW3Qm+q+dCb/CyMGCJ+b2 p73JyTNMtkYg9Nlw3l97r7BM9X0kE6v6Ndd+e7BM9EOhqvW3I4eUjOnixgWadV1OT4DJ vGmP9Pk6nJpZaKXNUSwQLLktQTX7p9gd6MgTCYdq8fQB0/dhPypdxVhWDxgzOFEbdc0Q BdlQ== X-Gm-Message-State: ABUngvfyaDguNQYHjpox8pH4Q/R4KTbnR5Gvzc7eGfs2kKyLJXZdA9XOfQRT8Vba1jjxlg== X-Received: by 10.99.116.15 with SMTP id p15mr23710233pgc.167.1477445209564; Tue, 25 Oct 2016 18:26:49 -0700 (PDT) Received: from chrisp-dl.atlnz.lc ([2001:df5:b000:22:a4a7:b31:c210:ddc6]) by smtp.gmail.com with ESMTPSA id ij5sm36231958pab.2.2016.10.25.18.26.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Oct 2016 18:26:49 -0700 (PDT) From: Chris Packham To: u-boot@lists.denx.de Date: Wed, 26 Oct 2016 14:26:08 +1300 Message-Id: <20161026012612.9479-7-judge.packham@gmail.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161026012612.9479-1-judge.packham@gmail.com> References: <20161026012612.9479-1-judge.packham@gmail.com> MIME-Version: 1.0 Cc: Luka Perkov , Scott Wood , Scott Wood , Stefan Roese , Chris Packham Subject: [U-Boot] [RFC PATCH v2 06/10] nand: pxa3xx: Increase READ_ID buffer and make the size static X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The read ID count should be made as large as the maximum READ_ID size, so there's no need to have dynamic size. This commit sets the hardware maximum read ID count, which should be more than enough on all cases. Also, we get rid of the read_id_bytes, and use a macro instead. [ Linux commit b226eca2088004622434cbcc27c6401b64f22d7c] Cc: Ezequiel García Signed-off-by: Chris Packham --- Changes in v2: - New drivers/mtd/nand/pxa3xx_nand.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index c97d85782cb1..d1c6e010f3c0 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -110,6 +110,13 @@ #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */ #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */ +/* + * This should be large enough to read 'ONFI' and 'JEDEC'. + * Let's use 7 bytes, which is the maximum ID count supported + * by the controller (see NDCR_RD_ID_CNT_MASK). + */ +#define READ_ID_BYTES 7 + /* macros for registers read/write */ #define nand_writel(info, off, val) \ writel((val), (info)->mmio_base + (off)) @@ -156,8 +163,6 @@ struct pxa3xx_nand_host { /* calculated from pxa3xx_nand_flash data */ unsigned int col_addr_cycles; unsigned int row_addr_cycles; - size_t read_id_bytes; - }; struct pxa3xx_nand_info { @@ -856,7 +861,7 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command, break; case NAND_CMD_READID: - info->buf_count = host->read_id_bytes; + info->buf_count = READ_ID_BYTES; info->ndcb0 |= NDCB0_CMD_TYPE(3) | NDCB0_ADDR_CYC(1) | command; @@ -1236,23 +1241,10 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info) static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) { - /* - * We set 0 by hard coding here, for we don't support keep_config - * when there is more than one chip attached to the controller - */ - struct pxa3xx_nand_host *host = info->host[0]; uint32_t ndcr = nand_readl(info, NDCR); - if (ndcr & NDCR_PAGE_SZ) { - /* Controller's FIFO size */ - info->chunk_size = 2048; - host->read_id_bytes = 4; - } else { - info->chunk_size = 512; - host->read_id_bytes = 2; - } - /* Set an initial chunk size */ + info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; info->reg_ndcr = ndcr & ~NDCR_INT_MASK; info->ndtr0cs0 = nand_readl(info, NDTR0CS0); info->ndtr1cs0 = nand_readl(info, NDTR1CS0); @@ -1282,7 +1274,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host) /* configure default flash values */ info->reg_ndcr = 0x0; /* enable all interrupts */ info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; - info->reg_ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); + info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */ /* use the common timing to make a try */ @@ -1499,7 +1491,6 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info) info->host[cs] = host; host->cs = cs; host->info_data = info; - host->read_id_bytes = 4; mtd->owner = THIS_MODULE; nand_set_controller_data(chip, host);