From patchwork Mon Sep 26 18:29:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 675283 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sjXcB6dzQz9s3T for ; Tue, 27 Sep 2016 04:31:38 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CD87BA7652; Mon, 26 Sep 2016 20:31:21 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id st5u6BJaDZ-5; Mon, 26 Sep 2016 20:31:21 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 43C85A75E4; Mon, 26 Sep 2016 20:31:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 31EA1A761F for ; Mon, 26 Sep 2016 20:31:19 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MlpF77B1iu3x for ; Mon, 26 Sep 2016 20:31:19 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailapp01.imgtec.com (mailapp02.imgtec.com [217.156.133.132]) by theia.denx.de (Postfix) with ESMTP id 06E5CA75E4 for ; Mon, 26 Sep 2016 20:31:17 +0200 (CEST) Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 3FE9E5FCB1135; Mon, 26 Sep 2016 19:31:13 +0100 (IST) Received: from localhost (10.100.200.111) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 26 Sep 2016 19:31:16 +0100 From: Paul Burton To: , Daniel Schwierzeck Date: Mon, 26 Sep 2016 19:29:01 +0100 Message-ID: <20160926182917.27531-8-paul.burton@imgtec.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20160926182917.27531-1-paul.burton@imgtec.com> References: <20160926182917.27531-1-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.111] Subject: [U-Boot] [PATCH 07/23] pci: Handle MIPS systems with virtual CONFIG_SYS_SDRAM_BASE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The decode_regions() function in the PCI code presumes that CONFIG_SYS_SDRAM_BASE is a physical address, which seems reasonable given that README states that it should be. However there is also common code which expects CONFIG_SYS_SDRAM_BASE to be an address accessible by the CPU, ie. a valid virtual address - notably gd->ram_top is set to it & various pieces of data are located relative to that, and getenv_bootm_low() defaults to CONFIG_SYS_SDRAM_BASE as the lower bound on addresses to load into. Thus on MIPS CONFIG_SYS_SDRAM_BASE is a virtual address. This patch takes the simple approach to fixing this & converts CONFIG_SYS_SDRAM_BASE to a physical address for use by the PCI code when built for MIPS. Signed-off-by: Paul Burton --- drivers/pci/pci-uclass.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 415c632..26fe0f4 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -848,7 +848,9 @@ static int decode_regions(struct pci_controller *hose, const void *blob, /* Add a region for our local memory */ size = gd->ram_size; -#ifdef CONFIG_SYS_SDRAM_BASE +#if defined(CONFIG_MIPS) + base = virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE); +#elif defined(CONFIG_SYS_SDRAM_BASE) base = CONFIG_SYS_SDRAM_BASE; #endif if (gd->pci_ram_top && gd->pci_ram_top < base + size)