From patchwork Mon Sep 26 18:28:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 675281 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sjXbj0NDfz9s3T for ; Tue, 27 Sep 2016 04:31:13 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D6581A75E4; Mon, 26 Sep 2016 20:30:54 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5AilNFg-4Hrp; Mon, 26 Sep 2016 20:30:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 50CF7A756F; Mon, 26 Sep 2016 20:30:54 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0F1AFA7577 for ; Mon, 26 Sep 2016 20:30:52 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ne9oAw7PB6r0 for ; Mon, 26 Sep 2016 20:30:51 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailapp01.imgtec.com (mailapp02.imgtec.com [217.156.133.132]) by theia.denx.de (Postfix) with ESMTP id 646DCA75FD for ; Mon, 26 Sep 2016 20:30:48 +0200 (CEST) Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 1FFD55D56B556; Mon, 26 Sep 2016 19:30:44 +0100 (IST) Received: from localhost (10.100.200.111) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 26 Sep 2016 19:30:47 +0100 From: Paul Burton To: , Daniel Schwierzeck Date: Mon, 26 Sep 2016 19:28:59 +0100 Message-ID: <20160926182917.27531-6-paul.burton@imgtec.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20160926182917.27531-1-paul.burton@imgtec.com> References: <20160926182917.27531-1-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.111] Subject: [U-Boot] [PATCH 05/23] pci: xilinx: Avoid writing memory base or limit registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Writing the PCI memory base & limit registers leads to the root bridge reporting a PCI_MEMORY_BASE value of 0 & a PCI_MEMORY_LIMIT value of 0x1600. If we then boot Linux, it sees that the bridge device needs 0x16000000 bytes of memory space & fails to assign it. It's unclear to me why this happens, and poking values from the shell doesn't seem to make anything clearer, but this workaround allows a MIPS Boston board to boot Linux & let Linux successfully probe the PCIe bus & all devices connected to it. Signed-off-by: Paul Burton --- drivers/pci/pcie_xilinx.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index 9059c41..0237bec 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -160,6 +160,15 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf, if (err < 0) return 0; + if (bdf == PCI_BDF(bus->seq, 0, 0)) { + switch (offset) { + case PCI_MEMORY_BASE: + case PCI_MEMORY_LIMIT: + /* Writing the memory base or limit causes problems */ + return 0; + } + } + switch (size) { case PCI_SIZE_8: __raw_writeb(value, address);