From patchwork Mon Sep 26 18:29:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 675289 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sjXdr5hjqz9s3T for ; Tue, 27 Sep 2016 04:33:04 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BF5D7A7558; Mon, 26 Sep 2016 20:32:50 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0w6emH_CM0a4; Mon, 26 Sep 2016 20:32:50 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 371B5A7631; Mon, 26 Sep 2016 20:32:50 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5779CA7558 for ; Mon, 26 Sep 2016 20:32:47 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5Kte_yFDO628 for ; Mon, 26 Sep 2016 20:32:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailapp01.imgtec.com (mailapp02.imgtec.com [217.156.133.132]) by theia.denx.de (Postfix) with ESMTP id 1F536A7544 for ; Mon, 26 Sep 2016 20:32:46 +0200 (CEST) Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id A042485AF0D42; Mon, 26 Sep 2016 19:32:41 +0100 (IST) Received: from localhost (10.100.200.111) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 26 Sep 2016 19:32:44 +0100 From: Paul Burton To: , Daniel Schwierzeck Date: Mon, 26 Sep 2016 19:29:07 +0100 Message-ID: <20160926182917.27531-14-paul.burton@imgtec.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20160926182917.27531-1-paul.burton@imgtec.com> References: <20160926182917.27531-1-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.111] Cc: Joe Hershberger Subject: [U-Boot] [PATCH 13/23] net: pch_gbe: Add cache maintenance X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is present. When there is no IOCU we need to writeback or invalidate the data caches at appropriate points. Perform this cache maintenance in the pch_gbe driver which is used on the MIPS Boston development board. Signed-off-by: Paul Burton Reviewed-by: Bin Meng Tested-by: Bin Meng --- drivers/net/pch_gbe.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index 1432351..8866f66 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -120,6 +120,8 @@ static void pch_gbe_rx_descs_init(struct udevice *dev) rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev, priv->rx_buff[i]); + flush_dcache_range((ulong)rx_desc, (ulong)&rx_desc[PCH_GBE_DESC_NUM]); + writel(dm_pci_virt_to_mem(priv->dev, rx_desc), &mac_regs->rx_dsc_base); writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1), @@ -137,6 +139,8 @@ static void pch_gbe_tx_descs_init(struct udevice *dev) memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM); + flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[PCH_GBE_DESC_NUM]); + writel(dm_pci_virt_to_mem(priv->dev, tx_desc), &mac_regs->tx_dsc_base); writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1), @@ -245,6 +249,8 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) u32 int_st; ulong start; + flush_dcache_range((ulong)packet, (ulong)packet + length); + tx_head = &priv->tx_desc[0]; tx_desc = &priv->tx_desc[priv->tx_idx]; @@ -258,6 +264,8 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) tx_desc->dma_status = 0; tx_desc->gbec_status = 0; + flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[1]); + /* Test the wrap-around condition */ if (++priv->tx_idx >= PCH_GBE_DESC_NUM) priv->tx_idx = 0; @@ -295,8 +303,12 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp) if (virt_to_phys(rx_desc) == hw_desc) return -EAGAIN; + /* Invalidate the descriptor */ + invalidate_dcache_range((ulong)rx_desc, (ulong)&rx_desc[1]); + length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN; buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0); + invalidate_dcache_range((ulong)buffer, (ulong)buffer + length); *packetp = (uchar *)buffer; return length;