From patchwork Mon Sep 26 07:08:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Albert ARIBAUD (3ADEV)" X-Patchwork-Id: 674978 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sjFTz5nZDz9ryZ for ; Mon, 26 Sep 2016 17:10:14 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 813A2B38E6; Mon, 26 Sep 2016 09:10:07 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lP-bmXCo2Jy3; Mon, 26 Sep 2016 09:10:07 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B2FBAB38F3; Mon, 26 Sep 2016 09:10:06 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4D873B38E5 for ; Mon, 26 Sep 2016 09:10:04 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6EI1UD3W0k5i for ; Mon, 26 Sep 2016 09:10:04 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp3-g21.free.fr (smtp3-g21.free.fr [212.27.42.3]) by theia.denx.de (Postfix) with ESMTPS id 18087B3896 for ; Mon, 26 Sep 2016 09:10:01 +0200 (CEST) Received: from localhost.localdomain (unknown [37.162.148.156]) (Authenticated sender: aribaud.smtp) by smtp3-g21.free.fr (Postfix) with ESMTPSA id 1AD5613F7E2; Mon, 26 Sep 2016 09:09:57 +0200 (CEST) From: "Albert ARIBAUD (3ADEV)" To: u-boot@lists.denx.de Date: Mon, 26 Sep 2016 09:08:07 +0200 Message-Id: <20160926070808.17021-6-albert.aribaud@3adev.fr> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160926070808.17021-5-albert.aribaud@3adev.fr> References: <20160926070808.17021-1-albert.aribaud@3adev.fr> <20160926070808.17021-2-albert.aribaud@3adev.fr> <20160926070808.17021-3-albert.aribaud@3adev.fr> <20160926070808.17021-4-albert.aribaud@3adev.fr> <20160926070808.17021-5-albert.aribaud@3adev.fr> Cc: "Albert ARIBAUD \(3ADEV\)" Subject: [U-Boot] [PATCH 5/6] pcm052: allow specifying onboard DDR size in configs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" PCM052 SoMs may be equipped with various sizes of DDR. Keep default of 256MB; new PCM052-based targets will specify their actual DDR size. Linux command line is auto-adjusted to DDR size. Signed-off-by: Albert ARIBAUD (3ADEV) --- board/phytec/pcm052/Kconfig | 4 ++++ include/configs/pcm052.h | 5 +++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig index d67a69a..88524a3 100644 --- a/board/phytec/pcm052/Kconfig +++ b/board/phytec/pcm052/Kconfig @@ -12,4 +12,8 @@ config SYS_SOC config SYS_CONFIG_NAME default "pcm052" +config PCM052_DDR_SIZE + int + default 256 + endif diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index cd235cc..b3e5054 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -135,7 +135,8 @@ "tftptimeout=1000\0" \ "tftptimeoutcountmax=1000000\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "bootargs_base=setenv bootargs rw mem=256M " \ + "bootargs_base=setenv bootargs rw " \ + " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ "console=ttyLP1,115200n8\0" \ "bootargs_sd=setenv bootargs ${bootargs} " \ "root=/dev/mmcblk0p2 rootwait\0" \ @@ -219,7 +220,7 @@ /* Physical memory map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR