From patchwork Fri Dec 25 13:41:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Sutter X-Patchwork-Id: 561027 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B9F29140C66 for ; Sat, 26 Dec 2015 00:46:33 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D66DA6211E; Fri, 25 Dec 2015 14:42:23 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q_M1MKv9AKCV; Fri, 25 Dec 2015 14:42:23 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F1D28B37D4; Fri, 25 Dec 2015 14:42:22 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6AA754BB52 for ; Fri, 25 Dec 2015 14:40:30 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fAUzGeqnqs-u for ; Fri, 25 Dec 2015 14:40:30 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.nwl.cc (orbyte.nwl.cc [151.80.46.58]) by theia.denx.de (Postfix) with ESMTPS id 40BEAA7498 for ; Fri, 25 Dec 2015 14:40:21 +0100 (CET) Received: from mail.nwl.cc (orbyte.nwl.cc [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id D40EC61224; Fri, 25 Dec 2015 14:40:15 +0100 (CET) Received: from base (localhost [IPv6:::1]) by mail.nwl.cc (Postfix) with ESMTP id B0E9E6121B; Fri, 25 Dec 2015 14:40:15 +0100 (CET) From: Phil Sutter To: u-boot@lists.denx.de Date: Fri, 25 Dec 2015 14:41:20 +0100 X-Mailer: git-send-email 2.5.3 In-Reply-To: <1451050886-20124-1-git-send-email-phil@nwl.cc> References: <1451050886-20124-1-git-send-email-phil@nwl.cc> Message-Id: <20151225134015.B0E9E6121B@mail.nwl.cc> X-Virus-Scanned: ClamAV using ClamSMTP Cc: Dennis Gilmore , Stefan Roese , Luka Perkov Subject: [U-Boot] [PATCH v3 04/10] drivers/pci/pci_mvebu: Fix for boards with X4 lanes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Armada XP has support for X4 lanes, boards specify this in their serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration is stored in GEN_PURP_RES_2_REG. When enumerating PEX, subsequent interfaces of an X4 lane must be skipped. Otherwise the enumeration hangs up the board. The way this is implemented here is not exactly beautiful, but it mimics how Marvell's BSP does it. Alternatively we could get the information using board_serdes_cfg_get(), but that won't lead to clean code, either. Signed-off-by: Phil Sutter Reviewed-by: Tom Rini --- arch/arm/mach-mvebu/include/mach/soc.h | 2 ++ drivers/pci/pci_mvebu.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 5d4ad30..9eaf0db 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -96,4 +96,6 @@ #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE +#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) + #endif /* _MVEBU_SOC_H */ diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index fd2744d..4eedfe1 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -155,6 +155,14 @@ static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, } #endif +static int mvebu_pex_unit_is_x4(int pex_idx) +{ + int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3; + u32 mask = (0x0f << (pex_unit * 8)); + + return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask; +} + static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) { u32 val; @@ -419,5 +427,11 @@ void pci_init_board(void) writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); bus = hose->last_busno + 1; + + /* need to skip more for X4 links, otherwise scan will hang */ + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + if (mvebu_pex_unit_is_x4(i)) + i += 3; + } } }