From patchwork Fri Dec 25 13:41:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Sutter X-Patchwork-Id: 561021 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9FC2B140C66 for ; Sat, 26 Dec 2015 00:42:32 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0C6974BB4D; Fri, 25 Dec 2015 14:40:40 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qFmSGyWhRqS2; Fri, 25 Dec 2015 14:40:39 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AB21FA749F; Fri, 25 Dec 2015 14:40:32 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3BF094BAFD for ; Fri, 25 Dec 2015 14:40:11 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gb0Co_ILJ9Mf for ; Fri, 25 Dec 2015 14:40:11 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.nwl.cc (orbyte.nwl.cc [151.80.46.58]) by theia.denx.de (Postfix) with ESMTPS id 0E6214BB10 for ; Fri, 25 Dec 2015 14:40:11 +0100 (CET) Received: from mail.nwl.cc (orbyte.nwl.cc [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 31F5D6121D; Fri, 25 Dec 2015 14:40:04 +0100 (CET) Received: from base (localhost [IPv6:::1]) by mail.nwl.cc (Postfix) with ESMTP id 060736121B; Fri, 25 Dec 2015 14:40:03 +0100 (CET) From: Phil Sutter To: u-boot@lists.denx.de Date: Fri, 25 Dec 2015 14:41:23 +0100 X-Mailer: git-send-email 2.5.3 In-Reply-To: <1451050886-20124-1-git-send-email-phil@nwl.cc> References: <1451050886-20124-1-git-send-email-phil@nwl.cc> Message-Id: <20151225134004.060736121B@mail.nwl.cc> X-Virus-Scanned: ClamAV using ClamSMTP Cc: Dennis Gilmore , Stefan Roese , Luka Perkov Subject: [U-Boot] [PATCH v3 07/10] mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This should make it clear that this symbol is meant to be defined by board headers. Signed-off-by: Phil Sutter Reviewed-by: Tom Rini --- drivers/ddr/marvell/axp/ddr3_axp_config.h | 2 +- drivers/ddr/marvell/axp/ddr3_axp_mc_static.h | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index 25c34fb..8549fe8 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -51,7 +51,7 @@ #define DRAM_ECC 0 #endif -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT #define BUS_WIDTH 32 #else #define BUS_WIDTH 64 diff --git a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h index 2c0e9075..71794ad 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h @@ -8,9 +8,9 @@ #define __AXP_MC_STATIC_H MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -66,9 +66,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ @@ -124,9 +124,9 @@ MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /* MV_DDR_64BIT */ +#else /* CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B840}, /*Dunit Control Low Register */ @@ -176,9 +176,9 @@ MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ #endif {0x00001404, 0x3630B040}, /*Dunit Control Low Register */ @@ -233,9 +233,9 @@ MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { }; MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = { -#ifdef MV_DDR_32BIT +#ifdef CONFIG_DDR_32BIT {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ -#else /*MV_DDR_64BIT */ +#else /*CONFIG_DDR_64BIT */ {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ /*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */ #endif