From patchwork Mon Dec 21 23:25:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Sutter X-Patchwork-Id: 559811 X-Patchwork-Delegate: prafulla@marvell.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 00618140291 for ; Tue, 22 Dec 2015 10:33:24 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 820E94B7F9; Tue, 22 Dec 2015 00:33:21 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t8Y94VjhdNNz; Tue, 22 Dec 2015 00:33:21 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2445A4B7FB; Tue, 22 Dec 2015 00:33:07 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 433D04B7CF for ; Tue, 22 Dec 2015 00:32:55 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uWHV4j95xgJB for ; Tue, 22 Dec 2015 00:32:54 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.nwl.cc (orbyte.nwl.cc [151.80.46.58]) by theia.denx.de (Postfix) with ESMTPS id 9530A4B7B1 for ; Tue, 22 Dec 2015 00:32:50 +0100 (CET) Received: from mail.nwl.cc (orbyte.nwl.cc [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 1D6C461215; Tue, 22 Dec 2015 00:24:40 +0100 (CET) Received: from base (localhost [IPv6:::1]) by mail.nwl.cc (Postfix) with ESMTP id ED1AB61201; Tue, 22 Dec 2015 00:24:39 +0100 (CET) From: Phil Sutter To: u-boot@lists.denx.de Date: Tue, 22 Dec 2015 00:25:52 +0100 X-Mailer: git-send-email 2.5.3 In-Reply-To: <1450740358-5014-1-git-send-email-phil@nwl.cc> References: <1450740358-5014-1-git-send-email-phil@nwl.cc> Message-Id: <20151221232439.ED1AB61201@mail.nwl.cc> X-Virus-Scanned: ClamAV using ClamSMTP Cc: Dennis Gilmore , Stefan Roese , Luka Perkov Subject: [U-Boot] [PATCH v2 2/8] mvebu: Fix for non-DM ehci-marvell support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This mimics the relevant code in mach-kirkwood headers. The *_winctrl_calcsize functions are identical, as well as the MVCPU_WIN_* macros. Implementing shared headers/code between mvebu and kirkwood is left for someone with a better knowledge of how u-boot is organized internally. Signed-off-by: Phil Sutter --- arch/arm/mach-mvebu/cpu.c | 21 +++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ arch/arm/mach-mvebu/include/mach/soc.h | 9 ++++++++- 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index c9b9c77..fd12c22 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -45,6 +45,27 @@ void reset_cpu(unsigned long ignored) ; } +/* + * Window Size + * Used with the Base register to set the address window size and location. + * Must be programmed from LSB to MSB as sequence of ones followed by + * sequence of zeros. The number of ones specifies the size of the window in + * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). + * NOTE: A value of 0x0 specifies 64-KByte size. + */ +unsigned int mvebu_winctrl_calcsize(unsigned int sizeval) +{ + int i; + unsigned int j = 0; + u32 val = sizeval >> 1; + + for (i = 0; val >= 0x10000; i++) { + j |= (1 << i); + val = val >> 1; + } + return 0x0000ffff & j; +} + int mvebu_soc_family(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 5e8bf0c..484638b 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -13,6 +13,9 @@ #ifndef __ASSEMBLY__ +#define MVEBU_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ + | (attr << 8) | (mvebu_winctrl_calcsize(size) << 16)) + #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 5d4ad30..cfc28c3 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -91,8 +91,15 @@ #define SDRAM_MAX_CS 4 #define SDRAM_ADDR_MASK 0xFF000000 +/* MVEBU USB Host controller */ +#define MVUSB0_BASE MVEBU_AXP_USB_BASE +#define MVUSB0_CPU_ATTR_DRAM_CS0 CPU_ATTR_DRAM_CS0 +#define MVUSB0_CPU_ATTR_DRAM_CS1 CPU_ATTR_DRAM_CS1 +#define MVUSB0_CPU_ATTR_DRAM_CS2 CPU_ATTR_DRAM_CS2 +#define MVUSB0_CPU_ATTR_DRAM_CS3 CPU_ATTR_DRAM_CS3 + /* MVEBU CPU memory windows */ -#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA +#define MVCPU_WIN_CTRL_DATA MVEBU_CPU_WIN_CTRL_DATA #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE