From patchwork Sun Dec 13 00:29:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Sutter X-Patchwork-Id: 556094 X-Patchwork-Delegate: prafulla@marvell.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5671D14031D for ; Sun, 13 Dec 2015 11:44:50 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F3ECC4B7C5; Sun, 13 Dec 2015 01:44:48 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RgMiE35RovPC; Sun, 13 Dec 2015 01:44:48 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 59CA24B792; Sun, 13 Dec 2015 01:44:48 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8EC4A4B6DE for ; Sun, 13 Dec 2015 01:35:13 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iW5m1DwR7uZB for ; Sun, 13 Dec 2015 01:35:13 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.nwl.cc (orbit.nwl.cc [176.31.251.142]) by theia.denx.de (Postfix) with ESMTPS id 5DC954B6D4 for ; Sun, 13 Dec 2015 01:35:09 +0100 (CET) Received: from mail.nwl.cc (orbit [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id E2D1021535 for ; Sun, 13 Dec 2015 01:28:56 +0100 (CET) Received: from base (orbit [IPv6:::1]) by mail.nwl.cc (Postfix) with ESMTP id BE93021533 for ; Sun, 13 Dec 2015 01:28:56 +0100 (CET) From: Phil Sutter To: u-boot@lists.denx.de Date: Sun, 13 Dec 2015 01:29:56 +0100 X-Mailer: git-send-email 2.5.3 In-Reply-To: <1449966599-25475-1-git-send-email-phil@nwl.cc> References: <1449966599-25475-1-git-send-email-phil@nwl.cc> Message-Id: <20151213002856.BE93021533@mail.nwl.cc> X-Virus-Scanned: ClamAV using ClamSMTP X-Mailman-Approved-At: Sun, 13 Dec 2015 01:44:46 +0100 Subject: [U-Boot] [PATCH 08/11] drivers/ddr/marvell: Default DRAM_ECC to 0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Not all boards implementing an Armada XP chip are equipped with ECC RAM. Defining DRAM_ECC to 1 enables ECC without a chance to turn it off in board configs, which breaks DDR training for them. Signed-off-by: Phil Sutter --- drivers/ddr/marvell/axp/ddr3_axp_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index a672044..800d2d1 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -44,7 +44,7 @@ * DDR3_TRAINING_DEBUG - Debug prints of internal code */ #define DDR_TARGET_FABRIC 5 -#define DRAM_ECC 1 +#define DRAM_ECC 0 #ifdef MV_DDR_32BIT #define BUS_WIDTH 32