From patchwork Sun Dec 13 00:29:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Sutter X-Patchwork-Id: 556097 X-Patchwork-Delegate: prafulla@marvell.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6E21514031D for ; Sun, 13 Dec 2015 11:45:19 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BABE94B842; Sun, 13 Dec 2015 01:45:11 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6LSfxmp72H_O; Sun, 13 Dec 2015 01:45:11 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 459B74B7FC; Sun, 13 Dec 2015 01:44:55 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2C07E4B76F for ; Sun, 13 Dec 2015 01:35:14 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JBOjxzcoY_iK for ; Sun, 13 Dec 2015 01:35:14 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.nwl.cc (orbit.nwl.cc [176.31.251.142]) by theia.denx.de (Postfix) with ESMTPS id F220E4B6D4 for ; Sun, 13 Dec 2015 01:35:13 +0100 (CET) Received: from mail.nwl.cc (orbit [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 56310214FB for ; Sun, 13 Dec 2015 01:28:45 +0100 (CET) Received: from base (orbit [IPv6:::1]) by mail.nwl.cc (Postfix) with ESMTP id 310EF20094 for ; Sun, 13 Dec 2015 01:28:45 +0100 (CET) From: Phil Sutter To: u-boot@lists.denx.de Date: Sun, 13 Dec 2015 01:29:54 +0100 X-Mailer: git-send-email 2.5.3 In-Reply-To: <1449966599-25475-1-git-send-email-phil@nwl.cc> References: <1449966599-25475-1-git-send-email-phil@nwl.cc> Message-Id: <20151213002845.310EF20094@mail.nwl.cc> X-Virus-Scanned: ClamAV using ClamSMTP X-Mailman-Approved-At: Sun, 13 Dec 2015 01:44:46 +0100 Subject: [U-Boot] [PATCH 06/11] drivers/pci/pci_mvebu: Fix for boards with X4 lanes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Armada XP has support for X4 lanes, boards specify this in their serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration is stored in GEN_PURP_RES_2_REG. When enumerating PEX, subsequent interfaces of an X4 lane must be skipped. Otherwise the enumeration hangs up the board. The way this is implemented here is not exactly beautiful, but it mimics how Marvell's BSP does it. Alternatively we could get the information using board_serdes_cfg_get(), but that won't lead to clean code, either. Especially since the ugly includes will have to be done anyway. Signed-off-by: Phil Sutter --- drivers/pci/pci_mvebu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index fd2744d..aab53f4 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -18,6 +18,11 @@ #include #include +#if defined(CONFIG_ARMADA_XP) +#include "../ddr/marvell/axp/ddr3_init.h" +#include "../../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h" +#endif + DECLARE_GLOBAL_DATA_PTR; /* PCIe unit register offsets */ @@ -155,6 +160,16 @@ static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, } #endif +#if defined(CONFIG_ARMADA_XP) +static int mvebu_pex_unit_is_x4(int pex_idx) +{ + int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3; + u32 mask = (0x0f << (pex_unit * 8)); + + return (reg_read(GEN_PURP_RES_2_REG) & mask) == mask; +} +#endif + static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) { u32 val; @@ -419,5 +434,11 @@ void pci_init_board(void) writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); bus = hose->last_busno + 1; + +#if defined(CONFIG_ARMADA_XP) + /* need to skip more for X4 links, otherwise scan will hang */ + if (mvebu_pex_unit_is_x4(i)) + i += 3; +#endif } }