From patchwork Mon May 17 06:28:22 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikhail Kshevetskiy X-Patchwork-Id: 71786 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: wd@gemini.denx.de Delivered-To: wd@gemini.denx.de Received: from diddl.denx.de (diddl.denx.de [10.0.0.6]) by gemini.denx.de (Postfix) with ESMTP id CF48CE6D663 for ; Mon, 17 May 2010 08:31:05 +0200 (CEST) Received: from diddl.denx.de (localhost.localdomain [127.0.0.1]) by diddl.denx.de (Postfix) with ESMTP id C0594C9203B9 for ; Mon, 17 May 2010 08:31:05 +0200 (CEST) Received: from pop.mnet-online.de by diddl.denx.de with POP3 (fetchmail-6.3.9) for (single-drop); Mon, 17 May 2010 08:31:05 +0200 (CEST) Received: from murder (svr19.m-online.net [192.168.3.147]) by backend2 (Cyrus v2.2.12) with LMTPA; Mon, 17 May 2010 08:28:48 +0200 X-Sieve: CMU Sieve 2.2 Received: from mail.m-online.net (localhost [127.0.0.1]) by frontend3.pop.m-online.net (Cyrus v2.2.13) with LMTPA; Mon, 17 May 2010 08:28:47 +0200 Received: from scanner-1.m-online.net (unknown [192.168.8.165]) by mail.m-online.net (Postfix) with ESMTP id ECB1C2001E3; Mon, 17 May 2010 08:28:47 +0200 (CEST) Received: from mxin-3.m-online.net ([192.168.6.165]) by scanner-1.m-online.net (scanner-1.m-online.net [192.168.8.165]) (amavisd-new, port 10026) with ESMTP id 15682-02-2; Mon, 17 May 2010 08:28:46 +0200 (CEST) Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by mxin-3.m-online.net (Postfix) with ESMTP id D87F447A4F7; Mon, 17 May 2010 08:28:45 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 76E5428089; Mon, 17 May 2010 08:28:42 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bTlDlz8YW9I1; Mon, 17 May 2010 08:28:42 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ABE522807C; Mon, 17 May 2010 08:28:36 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1753A28077 for ; Mon, 17 May 2010 08:28:34 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VlcRpxSXGSsb for ; Mon, 17 May 2010 08:28:32 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from fg-out-1718.google.com (fg-out-1718.google.com [72.14.220.152]) by theia.denx.de (Postfix) with ESMTP id 0D62A28071 for ; Mon, 17 May 2010 08:28:30 +0200 (CEST) Received: by fg-out-1718.google.com with SMTP id e12so1978383fga.9 for ; Sun, 16 May 2010 23:28:29 -0700 (PDT) Received: by 10.86.126.33 with SMTP id y33mr7806481fgc.51.1274077709268; Sun, 16 May 2010 23:28:29 -0700 (PDT) Received: from laska.campus-ws.pu.ru ([217.197.6.24]) by mx.google.com with ESMTPS id e3sm8976242fga.19.2010.05.16.23.28.28 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 May 2010 23:28:29 -0700 (PDT) Date: Mon, 17 May 2010 10:28:22 +0400 From: Mikhail Kshevetskiy To: Marek Vasut Message-ID: <20100517102822.50b2fa4b@laska.campus-ws.pu.ru> X-Mailer: Claws Mail 3.7.6 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Mime-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] arm/pxa-devel: fix and cleanup of pxa_mem_setup macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Virus-Scanned: by amavisd-new at m-online.net * strict following to section 6.4.10 of Intel PXA27xx Developer's Manual. * use r7 to store CONFIG_SYS_MDREFR_VAL as r6 is used in pxa_wait_ticks WARNING: This macro do not assume the values for K0DB4, KxDB2, KxFREE and APD bits of CONFIG_SYS_MDREFR_VAL as it was done early on many pxa platforms. All pxa developers that plan to use this macro should check the validity of their MDREFR values. Signed-off-by: Mikhail Kshevetskiy --- arch/arm/include/asm/arch-pxa/macro.h | 81 +++++++++++++++++++++++---------- 1 files changed, 56 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 1f1759b..26d7a8d 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -102,7 +102,11 @@ /* * This macro sets up the Memory controller of the PXA2xx CPU * - * Clobbered regs: r3, r4, r5 + * Clobbered regs: r3, r4, r5, r6, r7 + * + * See section 6.4.10 of Intel PXA2xx Processor Developer's Manual + * http://www.marvell.com/products/processors/applications/pxa_family/pxa_27x_dev_man.pdf + * http://www.marvell.com/products/processors/applications/pxa_family/PXA3xx_Developers_Manual.zip */ .macro pxa_mem_setup /* This comes handy when setting MDREFR */ @@ -149,27 +153,38 @@ */ /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. + * Before accessing MDREFR we need a valid DRI field. + * Also we must properly configure MDREFR[K0DB2] and MDREFR[K0DB4]. + * Optionaly we can set MDREFR[KxFREE] bits. + * So we set MDREFR to power on defaults + (DRI, K0DB2, K0DB4, KxFREE) + * fields from the config. + * + * WARNING: K0DB2 and K0DB4 bits are usually set, while KxFREE bits + * are usually unser. */ ldr r5, [r3, #MDREFR_OFFSET] - bic r5, r5, #0x0ff - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r6, r4 - lsl r4, #20 - lsr r4, #20 /* Get a valid DRI field */ + ldr r4, =( 0xFFF | MDREFR_K0DB4 | MDREFR_K0DB2 ) + orr r4, #( MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE ) + bic r5, r5, r4 /* clear DRI, K0DB2, K0DB4, KxFREE fields */ - orr r5, r5, r4 /* MDREFR user config with correct DRI */ + /* + * r3 is busy with MEMC_BASE, + * r4, r5, r6 used in pxa_wait_ticks and other places, + * so use r7 to store user specified MDREFR_VAL + */ + ldr r7, =CONFIG_SYS_MDREFR_VAL + and r4, r7, r4 + orr r5, r5, r4 /* use custom DRI, K0DB2, K0DB4, KxFREE */ orr r5, #MDREFR_K0RUN orr r5, #MDREFR_SLFRSH bic r5, #MDREFR_APD bic r5, #MDREFR_E1PIN + bic r5, #MDREFR_K1RUN + bic r5, #MDREFR_K2RUN str r5, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 5) Initialize Synchronous Static Memory (Flash/Peripherals) @@ -184,16 +199,29 @@ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL /* - * 6) Initialize SDRAM + * 6) Initialize SDRAM, + * also we must properly set MDREFR[K1DB2] and MDREFR[K2DB2] + * + * WARNING: K1DB2 and K2DB2 bits are usually set */ - bic r6, #MDREFR_SLFRSH - str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + and r4, r7, #( MDREFR_K1DB2 | MDREFR_K2DB2 ) + ldr r5, [r3, #MDREFR_OFFSET] + bic r5, #( MDREFR_K1DB2 | MDREFR_K2DB2 ) + orr r5, r5, r4 - orr r6, #MDREFR_E1PIN - str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + orr r5, #MDREFR_K1RUN + orr r5, #MDREFR_K2RUN + str r5, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] + + bic r5, #MDREFR_SLFRSH + str r5, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] + + orr r5, #MDREFR_E1PIN + str r5, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure @@ -246,14 +274,17 @@ ldr r4, [r3, #MDMRS_OFFSET] /* - * 11) Enable APD + * 11) Optionaly enable MDREFR[APD] + * + * WARNING: APD bit is usually set. */ - ldr r4, [r3, #MDREFR_OFFSET] - and r6, r6, #MDREFR_APD - orr r4, r4, r6 - str r4, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + and r7, #MDREFR_APD + ldr r5, [r3, #MDREFR_OFFSET] + bic r5, #MDREFR_APD + orr r5, r5, r7 + str r5, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] .endm /*