From patchwork Thu Aug 4 03:35:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= X-Patchwork-Id: 1663539 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=EDSmG/8/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LyvX66NDTz9s2R for ; Thu, 4 Aug 2022 13:36:06 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7E7D184614; Thu, 4 Aug 2022 05:35:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="EDSmG/8/"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 17E7E845F2; Thu, 4 Aug 2022 05:35:33 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,RDNS_NONE, SPF_HELO_PASS,SPF_PASS,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 834C484547 for ; Thu, 4 Aug 2022 05:35:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=weijie.gao@mediatek.com X-UUID: a02c6b89a27a4561868143dc2b812684-20220804 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=1KkTpgOq0funiRootpOZxPgu4rU6nWWYt4nUwJ99hUk=; b=EDSmG/8/tsClKn25S8uzNOh+T11jPhCHZ8gVzhMZTDaYHvVR3ua1tVBB71HPgJeDhsFyV4z99pOpeYCNPaykoThZ2XrAh6CVV6UuaOAiK5Q9rC1lmPzAk01oLKeOai+He/4T5nGLm9SDTJWayaHK7GD/7kWXrn3x3iUU3EdilGw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:34abffb7-9987-4e9b-baf9-1621882b7529, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32, CLOUDID:d9d52ed1-841b-4e95-ad42-8f86e18f54fc, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: a02c6b89a27a4561868143dc2b812684-20220804 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 490453620; Thu, 04 Aug 2022 11:35:23 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 4 Aug 2022 11:35:21 +0800 Received: from mcddlt001.gcn.mediatek.inc (10.19.240.15) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 4 Aug 2022 11:35:21 +0800 From: Weijie Gao To: CC: GSS_MTK_Uboot_upstream , "Joe Hershberger" , Ramon Fried , Weijie Gao Subject: [PATCH 06/31] net: mediatek: use a struct to cover variations of all SoCs Date: Thu, 4 Aug 2022 11:35:20 +0800 Message-ID: <1daf284821f5a3bc522646034792805b50a3b971.1659581119.git.weijie.gao@mediatek.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Using a single soc id to control different initialization and TX/RX flow for all SoCs is not extensible if more hardware variations are added in the future. This patch introduces a struct to replace the original mtk_soc to allow the driver be able handle newer hardwares. Signed-off-by: Weijie Gao Reviewed-by: Simon Glass --- drivers/net/mtk_eth.c | 50 +++++++++++++++++++++++++++++-------------- drivers/net/mtk_eth.h | 25 +++++++++++++++++++++- 2 files changed, 58 insertions(+), 17 deletions(-) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 4fe7ee0d36..92d2ea4f2a 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -142,11 +142,9 @@ enum mtk_switch { SW_MT7531 }; -enum mtk_soc { - SOC_MT7623, - SOC_MT7629, - SOC_MT7622, - SOC_MT7621 +struct mtk_soc_data { + u32 caps; + u32 ana_rgc3; }; struct mtk_eth_priv { @@ -171,7 +169,7 @@ struct mtk_eth_priv { int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, u16 val); - enum mtk_soc soc; + const struct mtk_soc_data *soc; int gmac_id; int force_mode; int speed; @@ -679,7 +677,7 @@ static int mt7530_setup(struct mtk_eth_priv *priv) u32 val, txdrv; int i; - if (priv->soc != SOC_MT7621) { + if (!MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { /* Select 250MHz clk for RGMII mode */ mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, ETHSYS_TRGMII_CLK_SEL362_5, 0); @@ -1108,9 +1106,8 @@ static int mtk_phy_probe(struct udevice *dev) static void mtk_sgmii_init(struct mtk_eth_priv *priv) { /* Set SGMII GEN2 speed(2.5G) */ - clrsetbits_le32(priv->sgmii_base + ((priv->soc == SOC_MT7622) ? - SGMSYS_GEN2_SPEED : SGMSYS_GEN2_SPEED_V2), - SGMSYS_SPEED_2500, SGMSYS_SPEED_2500); + setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, + SGMSYS_SPEED_2500); /* Disable SGMII AN */ clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, @@ -1182,7 +1179,8 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); } - if (priv->soc == SOC_MT7623) { + if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) && + !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { /* Lower Tx Driving for TRGMII path */ for (i = 0 ; i < NUM_TRGMII_CTRL; i++) mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i), @@ -1431,7 +1429,11 @@ static int mtk_eth_of_to_plat(struct udevice *dev) ofnode subnode; int ret; - priv->soc = dev_get_driver_data(dev); + priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev); + if (!priv->soc) { + dev_err(dev, "missing soc compatible data\n"); + return -EINVAL; + } pdata->iobase = (phys_addr_t)dev_remap_addr(dev); @@ -1544,11 +1546,27 @@ static int mtk_eth_of_to_plat(struct udevice *dev) return 0; } +static const struct mtk_soc_data mt7629_data = { + .ana_rgc3 = 0x128, +}; + +static const struct mtk_soc_data mt7623_data = { + .caps = MT7623_CAPS, +}; + +static const struct mtk_soc_data mt7622_data = { + .ana_rgc3 = 0x2028, +}; + +static const struct mtk_soc_data mt7621_data = { + .caps = MT7621_CAPS, +}; + static const struct udevice_id mtk_eth_ids[] = { - { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 }, - { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 }, - { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 }, - { .compatible = "mediatek,mt7621-eth", .data = SOC_MT7621 }, + { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, + { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data }, + { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data }, + { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data }, {} }; diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index 057ecfaabf..15c2030617 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -9,8 +9,31 @@ #ifndef _MTK_ETH_H_ #define _MTK_ETH_H_ -/* Frame Engine Register Bases */ #include + +enum mkt_eth_capabilities { + MTK_TRGMII_BIT, + MTK_TRGMII_MT7621_CLK_BIT, + + /* PATH BITS */ + MTK_ETH_PATH_GMAC1_TRGMII_BIT, +}; + +#define MTK_TRGMII BIT(MTK_TRGMII_BIT) +#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) + +/* Supported path present on SoCs */ +#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) + +#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) + +#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) + +#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) + +#define MT7623_CAPS (MTK_GMAC1_TRGMII) + +/* Frame Engine Register Bases */ #define PDMA_BASE 0x0800 #define GDMA1_BASE 0x0500 #define GDMA2_BASE 0x1500