From patchwork Fri Jul 29 15:18:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Schaefer X-Patchwork-Id: 654141 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3s1CH93Q0zz9t1M for ; Sat, 30 Jul 2016 01:25:57 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0CC2CA76F2; Fri, 29 Jul 2016 17:25:40 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id emW763fYXT8R; Fri, 29 Jul 2016 17:25:39 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 826CCA763D; Fri, 29 Jul 2016 17:25:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BDFDE4BA16 for ; Fri, 29 Jul 2016 17:25:27 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qcIAfyu53-Bv for ; Fri, 29 Jul 2016 17:25:26 +0200 (CEST) X-Greylist: delayed 372 seconds by postgrey-1.34 at theia; Fri, 29 Jul 2016 17:25:20 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from eu-smtp-delivery-185.mimecast.com (eu-smtp-delivery-185.mimecast.com [207.82.80.185]) by theia.denx.de (Postfix) with ESMTP id 1B0E9A75CE for ; Fri, 29 Jul 2016 17:25:19 +0200 (CEST) Received: from SDEMUCHB02.kontron.local (host-212-18-14-254.customer.m-online.net [212.18.14.254]) (Using TLS) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-80-0X8tJV_iOiGTN5bFfYsDUA-2; Fri, 29 Jul 2016 16:19:04 +0100 Received: from SDEMUCMB02.kontron.local ([fe80::45b3:76ed:59fe:3fed]) by SDEMUCHB02.kontron.local ([fe80::1e6:aa2f:691:659e%14]) with mapi id 14.03.0123.003; Fri, 29 Jul 2016 17:18:54 +0200 From: Thomas Schaefer To: "york.sun@nxp.com" Thread-Topic: timing_cfg_2 register in FSL DDR driver Thread-Index: AdHpq5lKbDxL7w9bR7OhDmiQ0wvmzQ== Date: Fri, 29 Jul 2016 15:18:54 +0000 Message-ID: <1BBC30BFBAE48D49A8C663EE5D39C03F01B7F0C2F8@SDEMUCMB02.kontron.local> Accept-Language: en-US, de-DE Content-Language: de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.50.139] MIME-Version: 1.0 X-MC-Unique: 0X8tJV_iOiGTN5bFfYsDUA-2 Cc: "u-boot@lists.denx.de" Subject: [U-Boot] timing_cfg_2 register in FSL DDR driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hi York, with commit 5605dc6135f6f26560ef3b0c6ebc5141c531179a you fix wr_lat bits of timing_cfg_2 register for FSL ddr driver. Unfortunately this fix is wrong as (wr_lat & 0x10) is already 5 bits. To make things clearer maybe it is better to set wr_lat this way Best regards, Thomas diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 1d5cec6..5840b9d 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num, | ((add_lat_mclk & 0xf) << 28) | ((cpo & 0x1f) << 23) | ((wr_lat & 0xf) << 19) - | ((wr_lat & 0x10) << 18) + | (((wr_lat & 0x10) >> 4) << 18) | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) | ((cke_pls & 0x7) << 6)