From patchwork Tue Dec 10 05:02:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1207053 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="uF0IY0RL"; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47XJLM5xHbz9sPh for ; Tue, 10 Dec 2019 22:51:23 +1100 (AEDT) Received: from phobos.denx.de (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 654D181676; Tue, 10 Dec 2019 12:50:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="uF0IY0RL"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4529181660; Tue, 10 Dec 2019 06:02:55 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MIME_BASE64_TEXT,RDNS_NONE,SPF_HELO_NONE, UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by phobos.denx.de (Postfix) with ESMTP id 5568481619 for ; Tue, 10 Dec 2019 06:02:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sam.shih@mediatek.com X-UUID: dbc636873c4e4825a302d72b35a4cac2-20191210 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=HLVqTgBj0Mz7FBdgdAW5RsSEd+/awKD1RAb+zEkdML4=; b=uF0IY0RLm/RXSNW4hAgKrYONKLNQbYimJ5IBC9xOBMfNDufXrlrgnwJGBbbtnyceUUfjtnQGt3ljh5/5tcFj4JL3VAYrswF0djb/XqjPPNF42OyW1nWeWrhWdUItR5KpTPmUVqgtfh4aArvivoHjrMnpGzcZoXpghbCc13/xc+c=; X-UUID: dbc636873c4e4825a302d72b35a4cac2-20191210 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1020994111; Tue, 10 Dec 2019 13:02:44 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 10 Dec 2019 13:02:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 10 Dec 2019 13:02:36 +0800 From: Sam Shih To: Tom Rini Subject: [U-boot,v2,05/10] clk: mediatek: fix clock-rate overflow problem Date: Tue, 10 Dec 2019 13:02:18 +0800 Message-ID: <1575954143-4129-6-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1575954143-4129-1-git-send-email-sam.shih@mediatek.com> References: <1575954143-4129-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Mailman-Approved-At: Tue, 10 Dec 2019 12:50:42 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, Sam Shih , Ryder Lee , GSS_MTK_Uboot_upstream Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean This patch fix clock-rate overflow problem in mediatek clock driver common part. Signed-off-by: Sam Shih Reviewed-by: Ryder Lee --- drivers/clk/mediatek/clk-mtk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 6c6b500d9b..9c30be994e 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -39,7 +39,7 @@ * this function is recursively called to find the parent to calculate * the accurate frequency. */ -static int mtk_clk_find_parent_rate(struct clk *clk, int id, +static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, const struct driver *drv) { struct clk parent = { .id = id, }; @@ -265,7 +265,7 @@ static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv, return rate; } -static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) +static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; @@ -287,7 +287,7 @@ static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) return mtk_factor_recalc_rate(fdiv, rate); } -static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) +static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux = &priv->tree->muxes[off];