From patchwork Tue Aug 13 16:59:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 1146523 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="ilYf16fA"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 467KXj5HsTz9sND for ; Wed, 14 Aug 2019 03:32:21 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 7A40FC22085; Tue, 13 Aug 2019 17:16:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C73D3C22035; Tue, 13 Aug 2019 17:16:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 84830C2203F; Tue, 13 Aug 2019 16:59:56 +0000 (UTC) Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by lists.denx.de (Postfix) with ESMTPS id BE504C21FBE for ; Tue, 13 Aug 2019 16:59:55 +0000 (UTC) Received: by mail-pf1-f194.google.com with SMTP id o70so6603922pfg.5 for ; Tue, 13 Aug 2019 09:59:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6v4YDTvfd/lT5W6pm2bIvqryFIbjz3oWna1WeAROCcY=; b=ilYf16fAiNNJgPup6Jt4S0TkbkqrB3IEqyvhhS6MLrQianVK3Uo7fJOdZ5/C4UveDl Xwz4ZJb27mMLaLJHfSBQxW4sO/34UavAHgWytI4duYRhUavnNS4ii5SqPaOCwfTsyl8J f/uWtDvmtfknWn4rsc+ki4OqrABuidBxMgYqAogRrkhc+xGqRusPEoN0gFJ7nnFFOWk2 fzwbVbGlYv2blVLyfBGu4Pyye6fk5E6XmE7u6kVJdoI/Z7XORu+79BodFOsw1l9a77JI 8zeXYu99hs+uPPgqJDGdTFmfFr5ndT+wopIX/RXncNR5ri1sgapqlroHQj5rZ4YYYCK3 FFxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6v4YDTvfd/lT5W6pm2bIvqryFIbjz3oWna1WeAROCcY=; b=gnadt5Uww13eZU2FoTOdg402hQ10eGgtqhNkzZDJU77Jt0/udGYIMOsEtbfhTfTTqw 7IkzdyAezxRtMAFQCOwLCNx5AI4a54KDEVJqbZq+HeU5NkEag9riWreF4bkasppkxbxE rbWKkufTehHqKgH4XJKX4Xjfr6ISBnu8qSOLZOzWAz429yi2STh7F3N0vgs7wY59oKpT 0Ju70/p+FdNOzoYuOvEH78N71Dmwp2/9LGuAr8DJvvtkLTE/+DWg9keyAxLujLRAQrpS ejU/asmNj+ZZaRYCJ7DN1ZAlhfS9WBRcP8ov2EPWbfcIv+r87R1oB8MjWrNK0Yzl3o00 jzoQ== X-Gm-Message-State: APjAAAWV1F7lHvMp6b4ivx9wPX9QALNxUrFnTLE08JWgbobTCnsQuJcZ K19S1Mny9ZnxXR16+JzcorNpnPVDttOdWw== X-Google-Smtp-Source: APXvYqzKKf+qUw6vRDfTbi04VXBiQJjH5wKLrcEecdDzb0YOc9Brv/v9RzFKvUnr5eadE2WombVVgA== X-Received: by 2002:a63:2b84:: with SMTP id r126mr36275436pgr.308.1565715594145; Tue, 13 Aug 2019 09:59:54 -0700 (PDT) Received: from gamma07.internal.sifive.com ([64.62.193.194]) by smtp.googlemail.com with ESMTPSA id w11sm6040857pfi.105.2019.08.13.09.59.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Aug 2019 09:59:53 -0700 (PDT) From: Sagar Shrikant Kadam To: u-boot@lists.denx.de, paul.walmsley@sifive.com, palmer@sifive.com, anup.patel@wdc.com, atish.patra@wdc.com, jagan@amarulasolutions.com, vigneshr@ti.com Date: Tue, 13 Aug 2019 09:59:31 -0700 Message-Id: <1565715571-26558-4-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565715571-26558-1-git-send-email-sagar.kadam@sifive.com> References: <1565715571-26558-1-git-send-email-sagar.kadam@sifive.com> Subject: [U-Boot] [U-BOOT PATCH 3/3] spi: riscv: use single bit mode for spi transfers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use the SPI controller in FU540-C000 soc in one bit mode, rather than using spi-tx-bus-width and spi-rx-bus-width passed from the device tree. This patch handles a case where controller mode in format register (0x40) is configured as per the width specified in the dt-node of the slave device. For instance if spi-tx-bus-width and spi-rx-bus-width in the flash device node in dt is set to 4 bit mode, the controller gets configured in QUAD mode, whereas the spi nor scan tries to read the JEDEC ID with the reg_proto set to SNOR_PROTO_1_1_1 and fails. Signed-off-by: Sagar Shrikant Kadam --- drivers/spi/spi-sifive.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 969bd4b..7cf3ea4 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -146,12 +146,7 @@ static void sifive_spi_prep_transfer(struct sifive_spi *spi, /* Number of wires ? */ cr &= ~SIFIVE_SPI_FMT_PROTO_MASK; - if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD)) - cr |= SIFIVE_SPI_FMT_PROTO_QUAD; - else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL)) - cr |= SIFIVE_SPI_FMT_PROTO_DUAL; - else - cr |= SIFIVE_SPI_FMT_PROTO_SINGLE; + cr |= SIFIVE_SPI_FMT_PROTO_SINGLE; /* SPI direction in/out ? */ cr &= ~SIFIVE_SPI_FMT_DIR;