From patchwork Tue Jun 18 15:47:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hancock X-Patchwork-Id: 1118410 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sedsystems.ca Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45T77Q56wTz9s7h for ; Wed, 19 Jun 2019 11:45:22 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 58357C21EFF; Wed, 19 Jun 2019 01:42:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0E284C22060; Wed, 19 Jun 2019 01:40:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 514D2C21F3E; Tue, 18 Jun 2019 15:47:41 +0000 (UTC) Received: from sed198n136.sedsystems.ca (sed198n136.SEDSystems.ca [198.169.180.136]) by lists.denx.de (Postfix) with ESMTPS id B8FF8C21F74 for ; Tue, 18 Jun 2019 15:47:40 +0000 (UTC) Received: from barney.sedsystems.ca (barney [198.169.180.121]) by sed198n136.sedsystems.ca with ESMTP id x5IFldiC004043 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Jun 2019 09:47:39 -0600 (CST) Received: from SED.RFC1918.192.168.sedsystems.ca (eng1n65.eng.sedsystems.ca [172.21.1.65]) by barney.sedsystems.ca (8.14.7/8.14.4) with ESMTP id x5IFlSkf013046 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 18 Jun 2019 09:47:31 -0600 From: Robert Hancock To: u-boot@lists.denx.de Date: Tue, 18 Jun 2019 09:47:15 -0600 Message-Id: <1560872836-21456-5-git-send-email-hancock@sedsystems.ca> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1560872836-21456-1-git-send-email-hancock@sedsystems.ca> References: <1560872836-21456-1-git-send-email-hancock@sedsystems.ca> X-Scanned-By: MIMEDefang 2.64 on 198.169.180.136 X-Mailman-Approved-At: Wed, 19 Jun 2019 01:40:48 +0000 Cc: michal.simek@xilinx.com Subject: [U-Boot] [PATCH 4/5] fpga: virtex2: Add additional clock cycles after DONE assertion X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some Xilinx FPGA configuration options can result in the startup sequence extending past the end of the FPGA bitstream. Continue applying CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure the startup sequence is complete, as recommended by Xilinx. Signed-off-by: Robert Hancock --- drivers/fpga/virtex2.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 2383c69..5028244 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -247,6 +247,7 @@ static int virtex2_slave_post(xilinx_virtex2_slave_selectmap_fns *fn, int cookie) { int ret_val = FPGA_SUCCESS; + int num_done = 0; unsigned long ts; /* @@ -264,12 +265,18 @@ static int virtex2_slave_post(xilinx_virtex2_slave_selectmap_fns *fn, /* * Check for successful configuration. FPGA INIT_B and DONE - * should both be high upon successful configuration. + * should both be high upon successful configuration. Continue pulsing + * clock with data set to all ones until DONE is asserted and for 8 + * clock cycles afterwards. */ ts = get_timer(0); - ret_val = FPGA_SUCCESS; - while (((*fn->done)(cookie) == FPGA_FAIL) || - (*fn->init)(cookie)) { + while (true) { + if ((*fn->done)(cookie) == FPGA_SUCCESS && + !((*fn->init)(cookie))) { + if (num_done++ >= 8) + break; + } + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n", __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); @@ -277,6 +284,11 @@ static int virtex2_slave_post(xilinx_virtex2_slave_selectmap_fns *fn, ret_val = FPGA_FAIL; break; } + (*fn->wdata) (0xff, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk) (false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk) (true, true, cookie); } if (ret_val == FPGA_SUCCESS) {