From patchwork Wed Apr 11 14:29:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 897210 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="OxqSIGku"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40Lmg91KZrz9s1j for ; Thu, 12 Apr 2018 00:31:01 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id CB03BC21D83; Wed, 11 Apr 2018 14:30:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A2901C21DF3; Wed, 11 Apr 2018 14:29:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A199CC21DD9; Wed, 11 Apr 2018 14:29:19 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id BF50EC21DA6 for ; Wed, 11 Apr 2018 14:29:15 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id u11so1991713wri.12 for ; Wed, 11 Apr 2018 07:29:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dSyviozOcXOg4WJB8Nf9B9B1JOxxdb5HZTJN949rF4s=; b=OxqSIGkusku+8ZymH0VwDg3oxyAHuCFz+rNtyhfb9AgtH9x0nmgPiU0JGeidhIJ3jK pzAICr4ivayn2esEBBFF6O7xP+jIt0wHngkb5iDo1HZgyIShPGwaZ7Op7dUwDmSihc7f XSk7OxtHdoMad4aBCRD0/FUaI/SgSdT7D1ViL3RHG/ks4jY/u5cVMNh2ibc1FGFkhL95 whfIFX+1K0fjCSFtJNzYtYq2niJY8qUcnu14q1U4KOOeECWOB2U32YHKTa7biE/mGvj8 Z4gYeshcJVCHDeoxfgQS64Qaye+lTJ6lKCbUeuGv8Gbn++x/KwlvUQFvUDDE4eeDbZSp CsHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dSyviozOcXOg4WJB8Nf9B9B1JOxxdb5HZTJN949rF4s=; b=lGbhII50y+3MsT77eKJBlCBZ6kZxqgVc4ND+gTMLATelL7RSAsIoKriOCRkg2EvHO8 CHDDecxVzFY+b2Ti89A1OJxmd+5OE4Iu+zFlWfync9in+tBF92MH0Vjxs4YH+jQalA60 jU4YHIQOlf5AK3SXNhNu3K1Rl5a7KocoSlXJJuvVCkpL/yFg+qLqmui7yLLalGFfZRVA BZ+KfDtmC7OlNDRXj11Uk5cqMRpT5iJDlvylmOCMfsCYgIGQgVdiMiKODp8BFWlayoiH gRVFjT6mG6BlYy++DA+Sp8rg/9JP6mfzqUS95FnS3RkU8Z9/I9/astAfEBOpcibiXvEX sM9g== X-Gm-Message-State: ALQs6tBWFImdBHCsaJbHSMT1XuunuvCwvqN2kBs+9QRSBcLaSTeYUHgt iWa4qLU5Qz9VTFJEtwv98hqe5FNtnmo= X-Google-Smtp-Source: AIpwx4+Q8n2rZdf/Hm+1u7+HAWOJGMTom4QYkUXBstorV6llSaUE/dM8L5OxVWQrEfb6WP/AmNUARQ== X-Received: by 10.223.165.66 with SMTP id j2mr2161886wrb.32.1523456954883; Wed, 11 Apr 2018 07:29:14 -0700 (PDT) Received: from bender.baylibre.local ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id k35sm1132575wre.55.2018.04.11.07.29.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Apr 2018 07:29:13 -0700 (PDT) From: Neil Armstrong To: u-boot@lists.denx.de, marex@denx.de, bmeng.cn@gmail.com Date: Wed, 11 Apr 2018 16:29:07 +0200 Message-Id: <1523456947-4242-4-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com> References: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com> Cc: linux-amlogic@lists.infradead.org Subject: [U-Boot] [PATCH v2 u-boot 3/3] phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Amlogic Meson GXL and GXM (simple variant) embeds up to 3 USB2 PHYs and an USB3 PHY. This patch adds drivers for these for the standard generic PHY interface and supports the power-on/off calls and set the Host mode by default. They are based on the excellent work from Martin Blumenstingl merged in linux. Signed-off-by: Neil Armstrong --- drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile | 1 + drivers/phy/meson-gxl-usb2.c | 238 +++++++++++++++++++++++++++++++++++++++++++ drivers/phy/meson-gxl-usb3.c | 201 ++++++++++++++++++++++++++++++++++++ 4 files changed, 448 insertions(+) create mode 100644 drivers/phy/meson-gxl-usb2.c create mode 100644 drivers/phy/meson-gxl-usb3.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 3b9a09c..99a6d95 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -85,4 +85,12 @@ config STI_USB_PHY used by USB2 and USB3 Host controllers available on STiH407 SoC families. +config MESON_GXL_USB_PHY + bool "Amlogic Meson GXL USB PHYs" + depends on PHY && ARCH_MESON && MESON_GXL + imply REGMAP + help + This is the generic phy driver for the Amlogic Meson GXL + USB2 and USB3 PHYS. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 668040b..6c1610e 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o +obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c new file mode 100644 index 0000000..15c9c89 --- /dev/null +++ b/drivers/phy/meson-gxl-usb2.c @@ -0,0 +1,238 @@ +/* + * Meson GXL and GXM USB2 PHY driver + * + * Copyright (C) 2017 Martin Blumenstingl + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 + #define U2P_R0_BYPASS_SEL BIT(0) + #define U2P_R0_BYPASS_DM_EN BIT(1) + #define U2P_R0_BYPASS_DP_EN BIT(2) + #define U2P_R0_TXBITSTUFF_ENH BIT(3) + #define U2P_R0_TXBITSTUFF_EN BIT(4) + #define U2P_R0_DM_PULLDOWN BIT(5) + #define U2P_R0_DP_PULLDOWN BIT(6) + #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) + #define U2P_R0_DP_VBUS_VLD_EXT BIT(8) + #define U2P_R0_ADP_PRB_EN BIT(9) + #define U2P_R0_ADP_DISCHARGE BIT(10) + #define U2P_R0_ADP_CHARGE BIT(11) + #define U2P_R0_DRV_VBUS BIT(12) + #define U2P_R0_ID_PULLUP BIT(13) + #define U2P_R0_LOOPBACK_EN_B BIT(14) + #define U2P_R0_OTG_DISABLE BIT(15) + #define U2P_R0_COMMON_ONN BIT(16) + #define U2P_R0_FSEL_MASK GENMASK(19, 17) + #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) + #define U2P_R0_POWER_ON_RESET BIT(22) + #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) + #define U2P_R0_ID_SET_ID_DQ BIT(25) + #define U2P_R0_ATE_RESET BIT(26) + #define U2P_R0_FSV_MINUS BIT(27) + #define U2P_R0_FSV_PLUS BIT(28) + #define U2P_R0_BYPASS_DM_DATA BIT(29) + #define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 + #define U2P_R1_BURN_IN_TEST BIT(0) + #define U2P_R1_ACA_ENABLE BIT(1) + #define U2P_R1_DCD_ENABLE BIT(2) + #define U2P_R1_VDAT_SRC_EN_B BIT(3) + #define U2P_R1_VDAT_DET_EN_B BIT(4) + #define U2P_R1_CHARGES_SEL BIT(5) + #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) + #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) + #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) + #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) + #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) + #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) + #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) + #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) + #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) + #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 + #define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0) + #define U2P_R2_TESTADDR_MASK GENMASK(11, 8) + #define U2P_R2_TESTDATA_OUT_SEL BIT(12) + #define U2P_R2_TESTCLK BIT(13) + #define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14) + #define U2P_R2_ACA_PIN_RANGE_C BIT(18) + #define U2P_R2_ACA_PIN_RANGE_B BIT(19) + #define U2P_R2_ACA_PIN_RANGE_A BIT(20) + #define U2P_R2_ACA_PIN_GND BIT(21) + #define U2P_R2_ACA_PIN_FLOAT BIT(22) + #define U2P_R2_CHARGE_DETECT BIT(23) + #define U2P_R2_DEVICE_SESSION_VALID BIT(24) + #define U2P_R2_ADP_PROBE BIT(25) + #define U2P_R2_ADP_SENSE BIT(26) + #define U2P_R2_SESSION_END BIT(27) + #define U2P_R2_VBUS_VALID BIT(28) + #define U2P_R2_B_VALID BIT(29) + #define U2P_R2_A_VALID BIT(30) + #define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { + struct regmap *regmap; +#if CONFIG_IS_ENABLED(DM_REGULATOR) + struct udevice *phy_supply; +#endif +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif +}; + +static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv) +{ + uint val; + + regmap_read(priv->regmap, U2P_R0, &val); + + /* reset the PHY and wait until settings are stabilized */ + val |= U2P_R0_POWER_ON_RESET; + regmap_write(priv->regmap, U2P_R0, val); + udelay(RESET_COMPLETE_TIME); + + val &= ~U2P_R0_POWER_ON_RESET; + regmap_write(priv->regmap, U2P_R0, val); + udelay(RESET_COMPLETE_TIME); +} + +static void +phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv) +{ + uint val; + + regmap_read(priv->regmap, U2P_R0, &val); + val |= U2P_R0_DM_PULLDOWN; + val |= U2P_R0_DP_PULLDOWN; + val &= ~U2P_R0_ID_PULLUP; + regmap_write(priv->regmap, U2P_R0, val); + + phy_meson_gxl_usb2_reset(priv); +} + +static int phy_meson_gxl_usb2_power_on(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, U2P_R0, &val); + /* power on the PHY by taking it out of reset mode */ + val &= ~U2P_R0_POWER_ON_RESET; + regmap_write(priv->regmap, U2P_R0, val); + + phy_meson_gxl_usb2_set_host_mode(priv); + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (priv->phy_supply) { + int ret = regulator_set_enable(priv->phy_supply, true); + if (ret) + return ret; + } +#endif + + return 0; +} + +static int phy_meson_gxl_usb2_power_off(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, U2P_R0, &val); + /* power off the PHY by putting it into reset mode */ + val |= U2P_R0_POWER_ON_RESET; + regmap_write(priv->regmap, U2P_R0, val); + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (priv->phy_supply) { + int ret = regulator_set_enable(priv->phy_supply, false); + if (ret) { + pr_err("Error disabling PHY supply\n"); + return ret; + } + } +#endif + + return 0; +} + +struct phy_ops meson_gxl_usb2_phy_ops = { + .power_on = phy_meson_gxl_usb2_power_on, + .power_off = phy_meson_gxl_usb2_power_off, +}; + +int meson_gxl_usb2_phy_probe(struct udevice *dev) +{ + struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); + int ret; + + ret = regmap_init_mem(dev, &priv->regmap); + if (ret) + return ret; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&priv->clk); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { + pr_err("failed to enable PHY clock\n"); + clk_free(&priv->clk); + return ret; + } +#endif + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply); + if (ret && ret != -ENOENT) { + pr_err("Failed to get PHY regulator\n"); + return ret; + } +#endif + + return 0; +} + +static const struct udevice_id meson_gxl_usb2_phy_ids[] = { + { .compatible = "amlogic,meson-gxl-usb2-phy" }, + { } +}; + +U_BOOT_DRIVER(meson_gxl_usb2_phy) = { + .name = "meson_gxl_usb2_phy", + .id = UCLASS_PHY, + .of_match = meson_gxl_usb2_phy_ids, + .probe = meson_gxl_usb2_phy_probe, + .ops = &meson_gxl_usb2_phy_ops, + .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv), +}; diff --git a/drivers/phy/meson-gxl-usb3.c b/drivers/phy/meson-gxl-usb3.c new file mode 100644 index 0000000..a385fbd --- /dev/null +++ b/drivers/phy/meson-gxl-usb3.c @@ -0,0 +1,201 @@ +/* + * Meson GXL USB3 PHY driver + * + * Copyright (C) 2018 Martin Blumenstingl + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define USB_R0 0x00 + #define USB_R0_P30_FSEL_MASK GENMASK(5, 0) + #define USB_R0_P30_PHY_RESET BIT(6) + #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7) + #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8) + #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9) + #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14) + #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) + #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) + #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19) + #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29) + #define USB_R0_U2D_ACT BIT(31) + +#define USB_R1 0x04 + #define USB_R1_U3H_BIGENDIAN_GS BIT(0) + #define USB_R1_U3H_PME_ENABLE BIT(1) + #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2) + #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7) + #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12) + #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16) + #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17) + #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18) + #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19) + #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25) + +#define USB_R2 0x08 + #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0) + #define USB_R2_P30_CR_READ BIT(16) + #define USB_R2_P30_CR_WRITE BIT(17) + #define USB_R2_P30_CR_CAP_ADDR BIT(18) + #define USB_R2_P30_CR_CAP_DATA BIT(19) + #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20) + #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26) + +#define USB_R3 0x0c + #define USB_R3_P30_SSC_ENABLE BIT(0) + #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1) + #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4) + #define USB_R3_P30_REF_SSP_EN BIT(13) + #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16) + #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19) + #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24) + +#define USB_R4 0x10 + #define USB_R4_P21_PORT_RESET_0 BIT(0) + #define USB_R4_P21_SLEEP_M0 BIT(1) + #define USB_R4_MEM_PD_MASK GENMASK(3, 2) + #define USB_R4_P21_ONLY BIT(4) + +#define USB_R5 0x14 + #define USB_R5_ID_DIG_SYNC BIT(0) + #define USB_R5_ID_DIG_REG BIT(1) + #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2) + #define USB_R5_ID_DIG_EN_0 BIT(4) + #define USB_R5_ID_DIG_EN_1 BIT(5) + #define USB_R5_ID_DIG_CURR BIT(6) + #define USB_R5_ID_DIG_IRQ BIT(7) + #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8) + #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16) + +/* read-only register */ +#define USB_R6 0x18 + #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0) + #define USB_R6_P30_CR_ACK BIT(16) + +struct phy_meson_gxl_usb3_priv { + struct regmap *regmap; +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif +}; + +static int +phy_meson_gxl_usb3_set_host_mode(struct phy_meson_gxl_usb3_priv *priv) +{ + uint val; + + regmap_read(priv->regmap, USB_R0, &val); + val &= ~USB_R0_U2D_ACT; + regmap_write(priv->regmap, USB_R0, val); + + regmap_read(priv->regmap, USB_R4, &val); + val &= ~USB_R4_P21_SLEEP_M0; + regmap_write(priv->regmap, USB_R4, val); + + return 0; +} + +static int phy_meson_gxl_usb3_power_on(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, USB_R5, &val); + val |= USB_R5_ID_DIG_EN_0; + val |= USB_R5_ID_DIG_EN_1; + val &= ~USB_R5_ID_DIG_TH_MASK; + val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff); + regmap_write(priv->regmap, USB_R5, val); + + return phy_meson_gxl_usb3_set_host_mode(priv); +} + +static int phy_meson_gxl_usb3_power_off(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, USB_R5, &val); + val &= ~USB_R5_ID_DIG_EN_0; + val &= ~USB_R5_ID_DIG_EN_1; + regmap_write(priv->regmap, USB_R5, val); + + return 0; +} + +static int phy_meson_gxl_usb3_init(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, USB_R1, &val); + val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK; + val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20); + regmap_write(priv->regmap, USB_R1, val); + + return 0; +} + +struct phy_ops meson_gxl_usb3_phy_ops = { + .init = phy_meson_gxl_usb3_init, + .power_on = phy_meson_gxl_usb3_power_on, + .power_off = phy_meson_gxl_usb3_power_off, +}; + +int meson_gxl_usb3_phy_probe(struct udevice *dev) +{ + struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); + int ret; + + ret = regmap_init_mem(dev, &priv->regmap); + if (ret) + return ret; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&priv->clk); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { + pr_err("failed to enable PHY clock\n"); + clk_free(&priv->clk); + return ret; + } +#endif + + return 0; +} + +static const struct udevice_id meson_gxl_usb3_phy_ids[] = { + { .compatible = "amlogic,meson-gxl-usb3-phy" }, + { } +}; + +U_BOOT_DRIVER(meson_gxl_usb3_phy) = { + .name = "meson_gxl_usb3_phy", + .id = UCLASS_PHY, + .of_match = meson_gxl_usb3_phy_ids, + .probe = meson_gxl_usb3_phy_probe, + .ops = &meson_gxl_usb3_phy_ops, + .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb3_priv), +};