| Message ID | 1519198823-5292-1-git-send-email-chin.liang.see@intel.com |
|---|---|
| State | Deferred |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | [U-Boot,1/2] arm: socfpga: cyclone5: Enable Macronix flash support | expand |
On 21.02.2018 08:40, chin.liang.see@intel.com wrote: > From: Chin Liang See <chin.liang.see@intel.com> > > Ensure "spi-flash" is added into compatible string when there is > NOR flash being instantiated in DTS. Discovered "sf probe" command > without argument would hit error if spi-flash compatible string > is missing. This has already been fixed 5 days ago. Simon > > Signed-off-by: Chin Liang See <chin.liang.see@intel.com> > --- > arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +- > arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- > arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts > index 2e2b71f..549024c 100644 > --- a/arch/arm/dts/socfpga_cyclone5_is1.dts > +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts > @@ -87,7 +87,7 @@ > u-boot,dm-pre-reloc; > #address-cells = <1>; > #size-cells = <1>; > - compatible = "n25q00"; > + compatible = "n25q00","spi-flash"; > reg = <0>; /* chip select */ > spi-max-frequency = <100000000>; > m25p,fast-read; > diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts > index 95a8e65..e30bf9a 100644 > --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts > +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts > @@ -98,7 +98,7 @@ > u-boot,dm-pre-reloc; > #address-cells = <1>; > #size-cells = <1>; > - compatible = "n25q00"; > + compatible = "n25q00","spi-flash"; > reg = <0>; /* chip select */ > spi-max-frequency = <100000000>; > m25p,fast-read; > diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts > index e3ae8a8..3e78038 100644 > --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts > +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts > @@ -68,7 +68,7 @@ > flash0: n25q00@0 { > #address-cells = <1>; > #size-cells = <1>; > - compatible = "n25q00"; > + compatible = "n25q00","spi-flash"; > reg = <0>; /* chip select */ > spi-max-frequency = <50000000>; > m25p,fast-read;
On Wed, 2018-02-21 at 10:34 +0100, Simon Goldschmidt wrote: > On 21.02.2018 08:40, chin.liang.see@intel.com wrote: > > > > From: Chin Liang See <chin.liang.see@intel.com> > > > > Ensure "spi-flash" is added into compatible string when there is > > NOR flash being instantiated in DTS. Discovered "sf probe" command > > without argument would hit error if spi-flash compatible string > > is missing. > This has already been fixed 5 days ago. > Nice and thanks for the patch. I was pulling from the source few days back for enabling the Macronix flash and bumping into this same issue. Thanks Chin Liang > Simon > > > > > > > Signed-off-by: Chin Liang See <chin.liang.see@intel.com> > > --- > > arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +- > > arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- > > arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +- > > 3 files changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts > > b/arch/arm/dts/socfpga_cyclone5_is1.dts > > index 2e2b71f..549024c 100644 > > --- a/arch/arm/dts/socfpga_cyclone5_is1.dts > > +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts > > @@ -87,7 +87,7 @@ > > u-boot,dm-pre-reloc; > > #address-cells = <1>; > > #size-cells = <1>; > > - compatible = "n25q00"; > > + compatible = "n25q00","spi-flash"; > > reg = <0>; /* chip select */ > > spi-max-frequency = <100000000>; > > m25p,fast-read; > > diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts > > b/arch/arm/dts/socfpga_cyclone5_socdk.dts > > index 95a8e65..e30bf9a 100644 > > --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts > > +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts > > @@ -98,7 +98,7 @@ > > u-boot,dm-pre-reloc; > > #address-cells = <1>; > > #size-cells = <1>; > > - compatible = "n25q00"; > > + compatible = "n25q00","spi-flash"; > > reg = <0>; /* chip select */ > > spi-max-frequency = <100000000>; > > m25p,fast-read; > > diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts > > b/arch/arm/dts/socfpga_cyclone5_socrates.dts > > index e3ae8a8..3e78038 100644 > > --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts > > +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts > > @@ -68,7 +68,7 @@ > > flash0: n25q00@0 { > > #address-cells = <1>; > > #size-cells = <1>; > > - compatible = "n25q00"; > > + compatible = "n25q00","spi-flash"; > > reg = <0>; /* chip select */ > > spi-max-frequency = <50000000>; > > m25p,fast-read;
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 2e2b71f..549024c 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -87,7 +87,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00","spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 95a8e65..e30bf9a 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -98,7 +98,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00","spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index e3ae8a8..3e78038 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -68,7 +68,7 @@ flash0: n25q00@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00","spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <50000000>; m25p,fast-read;