| Message ID | 1517927164-18197-7-git-send-email-jagan@amarulasolutions.com |
|---|---|
| State | Deferred |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | phy: sunxi: Add Allwinner sun4i USB PHY | expand |
On 02/06/2018 03:25 PM, Jagan Teki wrote: > Enable OTG device clkgate and reset for H3/H5 > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > Suggested-by: Jun Nie <jun.nie@linaro.org> > --- > Note: > Since the driver is dm-driver, we even add SOC changes based on > compatible or driver_data but here few of the reset and clock bits > and register offset memebers are in SOC includes files. > > I even try to add driver code by adding config structure in .data > but that eventually increasing size. > All these code will anyway move to clock and reset framework > once dm support added. > > arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + > drivers/usb/musb-new/sunxi.c | 24 ++++++++++++++++++------ > 2 files changed, 19 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > index d794e16..6569883 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > @@ -288,6 +288,7 @@ struct sunxi_ccm_reg { > #define AHB_GATE_OFFSET_USB_EHCI1 27 > #define AHB_GATE_OFFSET_USB_EHCI0 26 > #endif > +#define AHB_GATE_OFFSET_OTG_DEVICE 23 > #ifdef CONFIG_MACH_SUN50I > #define AHB_GATE_OFFSET_USB0 23 > #elif !defined(CONFIG_MACH_SUN8I_R40) > diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c > index 562d311..7d94936 100644 > --- a/drivers/usb/musb-new/sunxi.c > +++ b/drivers/usb/musb-new/sunxi.c > @@ -80,6 +80,8 @@ struct sunxi_glue { > struct musb_host_data mdata; > struct sunxi_ccm_reg *ccm; > struct device dev; > + u32 rst_bit; > + u32 clkgate_bit; Until we reach 256bit systems, this can be u8 [...]
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index d794e16..6569883 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -288,6 +288,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif +#define AHB_GATE_OFFSET_OTG_DEVICE 23 #ifdef CONFIG_MACH_SUN50I #define AHB_GATE_OFFSET_USB0 23 #elif !defined(CONFIG_MACH_SUN8I_R40) diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 562d311..7d94936 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -80,6 +80,8 @@ struct sunxi_glue { struct musb_host_data mdata; struct sunxi_ccm_reg *ccm; struct device dev; + u32 rst_bit; + u32 clkgate_bit; }; #define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev) @@ -269,10 +271,13 @@ static int sunxi_musb_init(struct musb *musb) musb->isr = sunxi_musb_interrupt; - setbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0); + setbits_le32(&glue->ccm->ahb_gate0, + BIT(AHB_GATE_OFFSET_USB0) | glue->clkgate_bit); #ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0); + setbits_le32(&glue->ccm->ahb_reset0_cfg, + BIT(AHB_GATE_OFFSET_USB0) | glue->rst_bit); #endif + sunxi_usb_phy_init(0); USBC_ConfigFIFO_Base(); @@ -367,10 +372,15 @@ static int musb_usb_probe(struct udevice *dev) pdata.power = 250; pdata.platform_ops = &sunxi_musb_ops; - if (!device_is_compatible(dev, "allwinner,sun8i-h3-musb")) + if (!device_is_compatible(dev, "allwinner,sun8i-h3-musb")) { pdata.config = &musb_config; - else + } else { pdata.config = &musb_config_h3; +#ifdef CONFIG_MACH_SUNXI_H3_H5 + glue->rst_bit = BIT(AHB_GATE_OFFSET_OTG_DEVICE); + glue->clkgate_bit = BIT(AHB_GATE_OFFSET_OTG_DEVICE); +#endif + } #ifdef CONFIG_USB_MUSB_HOST pdata.mode = MUSB_HOST; @@ -400,9 +410,11 @@ static int musb_usb_remove(struct udevice *dev) sunxi_usb_phy_exit(0); #ifdef CONFIG_SUNXI_GEN_SUN6I - clrbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0); + clrbits_le32(&glue->ccm->ahb_reset0_cfg, + BIT(AHB_GATE_OFFSET_USB0) | glue->rst_bit); #endif - clrbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0); + clrbits_le32(&glue->ccm->ahb_gate0, + BIT(AHB_GATE_OFFSET_USB0) | glue->clkgate_bit); free(host->host); host->host = NULL;
Enable OTG device clkgate and reset for H3/H5 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Suggested-by: Jun Nie <jun.nie@linaro.org> --- Note: Since the driver is dm-driver, we even add SOC changes based on compatible or driver_data but here few of the reset and clock bits and register offset memebers are in SOC includes files. I even try to add driver code by adding config structure in .data but that eventually increasing size. All these code will anyway move to clock and reset framework once dm support added. arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + drivers/usb/musb-new/sunxi.c | 24 ++++++++++++++++++------ 2 files changed, 19 insertions(+), 6 deletions(-)