From patchwork Mon Jan 29 17:44:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 867217 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="APEIMUnE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zVcNX6dYnz9s74 for ; Tue, 30 Jan 2018 04:45:16 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 95D56C21E37; Mon, 29 Jan 2018 17:45:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=BAD_ENC_HEADER, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3DD25C21DA2; Mon, 29 Jan 2018 17:45:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 51226C21DA5; Mon, 29 Jan 2018 17:45:07 +0000 (UTC) Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-he1eur01on0049.outbound.protection.outlook.com [104.47.0.49]) by lists.denx.de (Postfix) with ESMTPS id 744DAC21C29 for ; Mon, 29 Jan 2018 17:45:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=ipGOckYfuO6xiAenPS4hs0ChdLWVd4hJmBr4mFJkdNw=; b=APEIMUnEC4FSLKDg+xUa2V/l2dEKTz5t+CLjTpMrv/36gTVaeUmOHZRKl/WNowPnPsufsIrgcU/AHQmxQHd4G/Spk15/iutJC+X1fOu7onjFHSq3sSXjumnSqa2ynEd95X8/DGmts78CKw7ZXuMVf25xn0gSBnat2aCr3Ty1kEs= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=york.sun@nxp.com; Received: from localhost.localdomain (66.235.19.164) by AM4PR04MB2067.eurprd04.prod.outlook.com (2603:10a6:200:11::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.444.14; Mon, 29 Jan 2018 17:45:02 +0000 From: York Sun To: u-boot@lists.denx.de Date: Mon, 29 Jan 2018 09:44:33 -0800 Message-Id: <1517247880-14471-1-git-send-email-york.sun@nxp.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [66.235.19.164] X-ClientProxiedBy: CY4PR06CA0045.namprd06.prod.outlook.com (2603:10b6:903:77::31) To AM4PR04MB2067.eurprd04.prod.outlook.com (2603:10a6:200:11::17) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7916ae3a-ad58-41bc-6f0f-08d567400741 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(4534165)(4627221)(201703031133081)(201702281549075)(48565401081)(5600026)(4604075)(2017052603307)(7153060)(7193020); SRVR:AM4PR04MB2067; X-Microsoft-Exchange-Diagnostics: 1; AM4PR04MB2067; 3:3Nl6aVJSM/fK5eo2mkoh+Ok0GDKTNf3vt5n09GzVJQ74nbd0yUTsLncadc9OqKcqPy86ajLDrKvhSl+oTqzWOIZmg14szIj1DYHgloUm3wzdnTlfETD9ed2kO5uh8uXwdaqJw76wglO0+rjIBbjPr2DY1zl8bKn04x3+MAuFJxCy7Hm1Qir17rDkbU6j+v3qKkaqxYG1qO63xFADYTDgOYn5RSrciaUyHlIVsTiQCUsg+9vW+8vu1ciWRGpXkQwa; 25:iu8WoaEjsZcwP3vRr4lgjyddvN5CuFUhvNisuFiuKyTSQMstFcf9RStuulLN2NJutmcK40/dRPFsK4ezfYAZ6atexsdFz9aL2LNV05pEeQhhKNXMtCl605pvxWoT6uoSaHB2HDd/eelezhikIC4GSxYlx28AFB87c5HQXnotNtOQtvX1m1eQNFP8qz8oTsu//ONjY2lgd8mtUP9Vhk/MEzyQipcBblQoL+EJhNO0Ya+lvwm9GJ4GSCKVTH+WYRQXYxZxUhUjwzNSMH+fgywP+vtZwecPvvTaLAA+PpYPXBbwPIVOiwSRE8MjA0lWJUMK3dfigWUsZXlszzqGxZBr8A==; 31:FQFZDW0kY3uy8yB46/nabf0pQLHFtpFXJRABgadu1PaEL9w7jdyNT2KCVQ5gZIau03IGHvNOdwSfBfnCT5SERLsJ7p1j76cDD5DWHzK8tmpfefRr8O0QDlszBkmYK8ZqroGtF8HVjVIICUAzw3471fIFnlZaadxc6PBPEYySAZcjIwjalaXMmShFuz+1vNI41Cq6lqcc0ZK0qomlOO7CLzCTzZsrU+7Hc8Jdyqgg4Us= X-MS-TrafficTypeDiagnostic: AM4PR04MB2067: X-Microsoft-Exchange-Diagnostics: 1; AM4PR04MB2067; 20:wx9sLubx2dQIshfPc3undXANhw1wi2Q6JxfSDkH5KkoumTjbc0HBulPjU1613iT7RIE74UYxE5IpslulUAPgH+K2CpufurQxaomiPqXfr0lPvzM5ew9wYw+Ur5h5otxP/BDYBie6rx/L8GMo72xSgRZPxenxc2e32V0sVeY6c/YWMc0NIy/70uIFFH/tHLcQtHT3eia+7i95D+f6UKRJK9JCm549dDrE0SuR2WSPOGs5ofZLPv6g70gRKetVEWPZWAJQO1HnWuWSdeBWv10PRfiZYY4rSVJ6fYREKZxsASSUGjoJpOxW80TZjOxpsXsAwlD4s8nzlu3nq6dhkVBntWYsx+z+MkcktsgfAdFg21o3loS0zsRALTZ5NTY72M7H6MQPBmZwpG3lYwffjDj4TbTgfjGEwMfm6BhZl4GiHwwnE+JszR5zT2zj4VjPrpYFRNM8rExiZaRdnDmIkDq4MddX2lnpS/bLTzoEsPlXFXKfJPo0FxRnh/yafV7lzivY; 4:ZaYZAyLmmpKEdkgae0a8Cu2952IdH0ctNZD95Yxf7hnfVWBIBM+wwiYi8LxMC08KCEwioFeT02t0+Ivq2/x0ByASPeCnKxi9txpDWSjLiT9yUM4peate6KWsLGHmg/mnBguTq47I0KEXcqGj+8wlnrs+fAS0U6rcptnPdIm76tcPaHKUR516PVE/YBXyhN59cQLpvz4GlIywkIFLVsA/86opwyy7yrQLKhwyPLtdQ8GnFApbp1MSKUj2ZeVLxejSXcEo2x4MgLCcvxCKgkh1Cgx0Lgkx7wirVI08ud1tXH0o9AM6WHzhvWw6VeoCA7Cg X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040501)(2401047)(8121501046)(5005006)(10201501046)(93006095)(93001095)(3002001)(3231101)(944501161)(6055026)(6041288)(20161123562045)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(6072148)(201708071742011); SRVR:AM4PR04MB2067; BCL:0; PCL:0; RULEID:; SRVR:AM4PR04MB2067; X-Forefront-PRVS: 0567A15835 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(6069001)(376002)(366004)(346002)(396003)(39860400002)(39380400002)(199004)(189003)(54906003)(81166006)(316002)(52116002)(6506007)(6116002)(3846002)(305945005)(386003)(16586007)(7736002)(53936002)(6916009)(5660300001)(6486002)(186003)(16526019)(81156014)(51416003)(25786009)(4326008)(36756003)(8676002)(2906002)(26005)(86362001)(478600001)(575784001)(48376002)(50466002)(97736004)(68736007)(47776003)(2351001)(6512007)(50226002)(6666003)(8936002)(2361001)(106356001)(66066001)(105586002); DIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR04MB2067; H:localhost.localdomain; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM4PR04MB2067; 23:KGQxW/FpiABEoG0kJDDnavepGICHtbluTlcas8EeX?= PXk7s6J6vhcrqFiS1mB6l+DpDlQe/QzrOlFFn7nhp1RwtCnsN9dBwrx8edykVN87xxNwQpjddJ+mf1b7PGS0RzdL4rGB2xlLv5+5IWaT/+DwiqgeBpoT9wcEpOAfjjsQ+B/+LwIgP3kZ8jfcR+8Nhvt01ebri2MMZtSYhriIipbkne37PvN2ofa7dywADI3CDIhw549ZoD355NykiYyqvOgKanQQQvctym8XdggsAAa+7FQt/um9NnIfregfIXenOt0iSyWS58zfQpTHzPG6IBL2JWaQuEP0VgLXLjPnawCvZlvJwYaTMxSmm/mtoElOz3p1t+FJqFUkOlSzqWu96XSgwpt8kXfliXQrpLBaR/ZEBeuNcrcoG4iFqIT5KL7UZ+V3zwD0+QStVf4Cd+DI1gLCRPf+jqIx+dyxggbEzSrY86eiVfQvLrnwbryAmTV8T0W0dBMN7e1MJK837etbdgAe+Oqaz5YgLEjyX7lcVXqYjmWxU/B3CUbGV/UVF+rAKvL2zhv/ewGSiWkLSWlb7i+Zm/Z8CaKJI4o+7+CYKr6tTonLT0Dqn4MPUaiaJocgPJeMAqYtFY3SeCiABOvfwyvVIo+dnoNJjsygmaaUwqq4WYpDC0vQT5iO0mKbh9iniFuiJ0Gbk9YX4lz201vzQDZDrqu256vM6u1fHegx4adfVxx6H/ZYp/VKymNeE8dgd1YuBVWSpiI45m3isfkyc9WWlw/jNIiOt2dIgnzXXr23zeJp3bFPkmNWU96dhpypB8K4izmHZr+YmPlelZd8/UvFDvtPaVY8bz/cDXDpKCrGnW0uxfDqtVIrD1Su0LZ1WWi6WYdiEQg7RY8siarm+zv5WDzg4Z7qGYCkKPZqmYMWckhN1a7j7N9Kmbg5KiIpxoOeGXF9gpmZdGMlE8YgYAvPFhSmUGgCCUKZKl3Z3UBMTTBxZMUY0Jd0+PpXm3yniX5y82kzwj9sjCb57ivP1ncgxoaLfspo5QUk/OR9m2CuKA3ZxEu2uHu/zudekeRcuwamFrHSnkOmykJfJh+c2OD1ifqAkX1FeJh4qO7gQaZHGc6myl02NP5HwjBUMFvs3uQ1LIA4v+C9I0mrPLl8sFS8GgyhMznxdNhbdIrYLbTPg== X-Microsoft-Exchange-Diagnostics: 1; AM4PR04MB2067; 6:dZkZnJE6ejbFTK6zX6eLKQaDnFriY5Gxsnf4IC3sH894puqKUoTUfoFz0NxES9lYBePELQ9Dad3dwihni2YjdmHe9m225I4iZwzA/xA1lL+LDhHmUZs1jDz4hozgIJBnOpc+0VkzzMiRY/SBuS+HoXD/8UJukG0iodEMtaStVjUv13EnManUmvsCunRr0TMsiCH70MjwR8bRXQVduBLitXM3STUtWwjBROVJgSOnOr8FD54vmt1raUbteqxGDFMWLFn5SRdcSLGaGQ+Ga2p8tsHtxJDRhbbog5ST1neDnmZwvMuXTc1Znq7qXyMdOpv9BHKKtvZNrrP7K04jL4RAVMU4bGoG9dNu3hZ7j2iF1pU=; 5:55Lz1X8JhNZALY5rOrV5v88lyMFyVBKuUI3u0nzQSPdoBvFNoLPxy2HNnhtYdtP+B53olS42IUi+jUDFIFboi5c8HjUXe0TFKUchjq2yqlQWHZ6MUqUvpPJ0fgDZ/bvPQeDCVLe2Y9KkzV9WlI8erId4YLXA4kALDMCL0U38I34=; 24:4LaotE2DFpIyYTqGBKiuh0AhfpmBewWFvCLn4RVsqNmgGcLZmX/qqmNe4iiuYMkDZ9kkHqALtnILINwS9m0pek/ZK0s7xbh/Z11tn+6JT9o=; 7:NIluMjw0FdeGKxs/nKItZxXNPfUngnhkdUjcMyzQOQvlA/watGZMXXm3sscqUtM6lT1qfARyLM4ebAn8GdR51QbWgP0m0fdiZCeHfeiQY79nTljF9FpJ+FydHvKB+foODYdz08gighsEdeM5RW6lfUezKIkv+FQTyrwMx0HBQFCFT+c6mIh0k1/gJLwT35UgsKPNofilJHoHnnRkO+Jm4fM4nU1RRsPKYQefJOsrXDpZVuvtO5sZ89sfMam8Hze1 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2018 17:45:02.9620 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7916ae3a-ad58-41bc-6f0f-08d567400741 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR04MB2067 Subject: [U-Boot] [PATCH v4 1/8] drivers/ddr/fsl: Fix DDR4 RDIMM support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For DDR4, command/address delay in mode registers and parity latency in timing config register are only needed for UDIMMs, but not RDIMMs. Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix calculation of timing config registers. Use hexadecimal format for printing RCW (register control word) registers. Signed-off-by: York Sun --- Changes in v4: Fix calculation of timing_cfg_7 using rcw_2 Fix calculation of timing_cfg_8 Changes in v3: None Changes in v2: None drivers/ddr/fsl/ctrl_regs.c | 51 +++++++++++++++++++++++--------------- drivers/ddr/fsl/ddr4_dimm_params.c | 2 ++ drivers/ddr/fsl/interactive.c | 9 +++++-- include/fsl_ddr_sdram.h | 1 + 4 files changed, 41 insertions(+), 22 deletions(-) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index c0ee858..33adfb1 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -732,6 +732,7 @@ static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, if (popts->rcw_override) { ddr->ddr_sdram_rcw_1 = popts->rcw_1; ddr->ddr_sdram_rcw_2 = popts->rcw_2; + ddr->ddr_sdram_rcw_3 = popts->rcw_3; } else { ddr->ddr_sdram_rcw_1 = common_dimm->rcw[0] << 28 | \ @@ -752,8 +753,12 @@ static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, common_dimm->rcw[14] << 4 | \ common_dimm->rcw[15]; } - debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); - debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); + debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", + ddr->ddr_sdram_rcw_1); + debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", + ddr->ddr_sdram_rcw_2); + debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n", + ddr->ddr_sdram_rcw_3); } } @@ -1159,8 +1164,14 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, esdmode5 = 0x00000400; /* Data mask enabled */ } - /* set command/address parity latency */ - if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + /* + * For DDR3, set C/A latency if address parity is enabled. + * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is + * handled by register chip and RCW settings. + */ + if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && + ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) || + !popts->registered_dimm_en)) { if (mclk_ps >= 935) { /* for DDR4-1600/1866/2133 */ esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; @@ -1193,7 +1204,9 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, esdmode5 = 0x00000400; } - if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && + ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) || + !popts->registered_dimm_en)) { if (mclk_ps >= 935) { /* for DDR4-1600/1866/2133 */ esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; @@ -1965,6 +1978,7 @@ static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) static void set_timing_cfg_7(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, const common_timing_params_t *common_dimm) { unsigned int txpr, tcksre, tcksrx; @@ -1975,16 +1989,11 @@ static void set_timing_cfg_7(const unsigned int ctrl_num, tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); - if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { - if (mclk_ps >= 935) { - /* parity latency 4 clocks in case of 1600/1866/2133 */ - par_lat = 4; - } else if (mclk_ps >= 833) { - /* parity latency 5 clocks for DDR4-2400 */ - par_lat = 5; - } else { - printf("parity: mclk_ps = %d not supported\n", mclk_ps); - } + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN && + CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) { + /* for DDR4 only */ + par_lat = (popts->rcw_2 & 0xf) + 1; + debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps); } cs_to_cmd = 0; @@ -2024,11 +2033,11 @@ static void set_timing_cfg_8(const unsigned int ctrl_num, const common_timing_params_t *common_dimm, unsigned int cas_latency) { - unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg; + int rwt_bg, wrt_bg, rrt_bg, wwt_bg; unsigned int acttoact_bg, wrtord_bg, pre_all_rec; - unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); - unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + - ((ddr->timing_cfg_2 & 0x00040000) >> 14); + int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); + int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + + ((ddr->timing_cfg_2 & 0x00040000) >> 14); rwt_bg = cas_latency + 2 + 4 - wr_lat; if (rwt_bg < tccdl) @@ -2130,6 +2139,8 @@ static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, rd_pre = popts->quad_rank_present ? 1 : 0; ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; + /* Disable MRS on parity error for RDIMMs */ + ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0; debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); } @@ -2535,7 +2546,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, #ifdef CONFIG_SYS_FSL_DDR4 set_ddr_sdram_cfg_3(ddr, popts); set_timing_cfg_6(ddr); - set_timing_cfg_7(ctrl_num, ddr, common_dimm); + set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm); set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); set_timing_cfg_9(ddr); set_ddr_dq_mapping(ddr, dimm_params); diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index 42834ca..6e26ba8 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -179,6 +179,8 @@ unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, case DDR4_SPD_MODULETYPE_RDIMM: /* Registered/buffered DIMMs */ pdimm->registered_dimm = 1; + if (spd->mod_section.registered.reg_map & 0x1) + pdimm->mirrored_dimm = 1; break; case DDR4_SPD_MODULETYPE_UDIMM: diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index c99bd2f..660060d 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -558,6 +558,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, */ CTRL_OPTIONS(twot_en), CTRL_OPTIONS(threet_en), + CTRL_OPTIONS(mirrored_dimm), CTRL_OPTIONS(ap_en), CTRL_OPTIONS(x4_en), CTRL_OPTIONS(bstopre), @@ -568,6 +569,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(rcw_override), CTRL_OPTIONS(rcw_1), CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS(rcw_3), CTRL_OPTIONS(ddr_cdr1), CTRL_OPTIONS(ddr_cdr2), CTRL_OPTIONS(tfaw_window_four_activates_ps), @@ -660,6 +662,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) CFG_REGS(ddr_sr_cntr), CFG_REGS(ddr_sdram_rcw_1), CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_sdram_rcw_3), CFG_REGS(ddr_cdr1), CFG_REGS(ddr_cdr2), CFG_REGS(dq_map_0), @@ -750,6 +753,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, CFG_REGS(ddr_sr_cntr), CFG_REGS(ddr_sdram_rcw_1), CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_sdram_rcw_3), CFG_REGS(ddr_cdr1), CFG_REGS(ddr_cdr2), CFG_REGS(dq_map_0), @@ -857,8 +861,9 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(wrlvl_start), CTRL_OPTIONS_HEX(cswl_override), CTRL_OPTIONS(rcw_override), - CTRL_OPTIONS(rcw_1), - CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS_HEX(rcw_1), + CTRL_OPTIONS_HEX(rcw_2), + CTRL_OPTIONS_HEX(rcw_3), CTRL_OPTIONS_HEX(ddr_cdr1), CTRL_OPTIONS_HEX(ddr_cdr2), CTRL_OPTIONS(tfaw_window_four_activates_ps), diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 6a1f04b..de7ef9b 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -408,6 +408,7 @@ typedef struct memctl_options_s { unsigned int rcw_override; unsigned int rcw_1; unsigned int rcw_2; + unsigned int rcw_3; /* control register 1 */ unsigned int ddr_cdr1; unsigned int ddr_cdr2;