From patchwork Wed Oct 18 08:02:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 827489 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="nxwGqC17"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yH4LF6FLsz9t39 for ; Wed, 18 Oct 2017 19:03:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 9DBBDC21DBA; Wed, 18 Oct 2017 08:02:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6E572C21D6A; Wed, 18 Oct 2017 08:02:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CF326C21C41; Wed, 18 Oct 2017 08:02:19 +0000 (UTC) Received: from mail-wm0-f49.google.com (mail-wm0-f49.google.com [74.125.82.49]) by lists.denx.de (Postfix) with ESMTPS id 6B57CC21C2B for ; Wed, 18 Oct 2017 08:02:19 +0000 (UTC) Received: by mail-wm0-f49.google.com with SMTP id f4so8407739wme.0 for ; Wed, 18 Oct 2017 01:02:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+NxLgViG2fC8qdKAp5Gx3WGvuOo4bw2RsqW3YnbyC58=; b=nxwGqC17EbItCvWmZSfkAKotwQCo3muV038tTY48AyPD11I8BEfyGcX3da2NklzmUn ariZcRWhARF/MzJCKbxpmOncERYnEtalLTMBfcWGSVVMApp6+in7yg4FQtEfOtQ5SBt2 N3o6Akh3MhqBlnfa7Yu0awIxJlHCghgfhkCzYBcXm4q2ajcUaGz0OqjAGH8vB55kuWH9 Z4TX0uEF01y6wOnFVXVc1JfjYsQVTqmGbf3JHzSRqKsKkhvGIhPp1eOjIiqZ/OSExm6+ fPFEGG1k+XOsvdUyganizUzUAl+w+s+Ta9B1fmzHII/XBp1JWHWLYxEQ+gBFstzLMpYy hGrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+NxLgViG2fC8qdKAp5Gx3WGvuOo4bw2RsqW3YnbyC58=; b=mp2kW4wQpUApEtCum+vzZym/ZXCxEuK1ResYCjLCnfU2erC5DVDuI57vft5a965hta QJb8ZTnPQ+50W6SE/+jzTMBxgjZ1tjZrP4S7aZPL29Zh/RcjQ1UBp1WkXLSssu/h9HR0 DnVarRn8yT0yfuG4KkkVfQ4Kcf2EKHVm2ZgRI7EB3iy09TCORolMlU9OqIhW8xrruBsN I2iSmwOYmg5ssclCE5dOmB8P1JkkvjWg3Laaii0k8AatxSGGDRF1G0RYF30/tPQCZY7v LRcPtalTLMRT4g18Jrq5Z8tfi837IMeYByQX3CE5K2LlJrkjFMXwoNMk++q48ZaKGY93 rJEg== X-Gm-Message-State: AMCzsaX91EiQyr/FB+/XtgiPV7HRgm43qHktWKR4/j+JMQoaFa9JIpxL fQIyeVwJpgp+oRzxg0+b/1OoaTSHs14= X-Google-Smtp-Source: ABhQp+SKt7vK6g35QiIEzmjKGwUeWYBVD+Vh5P079+qA+VMvcNpPITcOGZFQBvoIRdRYDw4PRA7VYg== X-Received: by 10.28.185.75 with SMTP id j72mr5824722wmf.138.1508313738686; Wed, 18 Oct 2017 01:02:18 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id v8sm8693254wrg.80.2017.10.18.01.02.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 01:02:17 -0700 (PDT) From: Neil Armstrong To: u-boot@lists.denx.de, albert.u.boot@aribaud.net, joe.hershberger@ni.com Date: Wed, 18 Oct 2017 10:02:10 +0200 Message-Id: <1508313732-19282-2-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508313732-19282-1-git-send-email-narmstrong@baylibre.com> References: <1508313732-19282-1-git-send-email-narmstrong@baylibre.com> Cc: trini@konsulko.com, linux-amlogic@lists.infradead.org Subject: [U-Boot] [PATCH u-boot 1/3] net: phy: Add Amlogic Meson GXL Internal PHY support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Amlogic Meson GXL/GXM families embeds an internal RMII Ethernet PHY. The PHY acts as a generic PHY but needs a slight configuration right before it's configuration. Signed-off-by: Neil Armstrong --- drivers/net/phy/Kconfig | 3 +++ drivers/net/phy/Makefile | 1 + drivers/net/phy/meson-gxl.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 +++ include/phy.h | 1 + 5 files changed, 65 insertions(+) create mode 100644 drivers/net/phy/meson-gxl.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 4d02d8b..e32f1eb 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -55,6 +55,9 @@ config PHY_LXT config PHY_MARVELL bool "Marvell Ethernet PHYs support" +config PHY_MESON_GXL + bool "Amlogic Meson GXL Internal PHY support" + config PHY_MICREL bool "Micrel Ethernet PHYs support" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 54f32f6..1e264b2 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PHY_LXT) += lxt.o obj-$(CONFIG_PHY_MARVELL) += marvell.o obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o +obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c new file mode 100644 index 0000000..ccf70c9 --- /dev/null +++ b/drivers/net/phy/meson-gxl.c @@ -0,0 +1,57 @@ +/* + * Meson GXL Internal PHY Driver + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * Copyright (C) 2016 BayLibre, SAS. All rights reserved. + * Author: Neil Armstrong + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include + +static int meson_gxl_phy_config(struct phy_device *phydev) +{ + /* Enable Analog and DSP register Bank access by */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + + /* Write Analog register 23 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417); + + /* Enable fractional PLL */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B); + + /* Program fraction FR_PLL_DIV1 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D); + + /* Program fraction FR_PLL_DIV1 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C); + + return genphy_config(phydev); +} + +static struct phy_driver meson_gxl_phy_driver = { + .name = "Meson GXL Internal PHY", + .uid = 0x01814400, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &meson_gxl_phy_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_meson_gxl_init(void) +{ + phy_register(&meson_gxl_phy_driver); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 5be51d7..fd3dd55 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -494,6 +494,9 @@ int phy_init(void) #ifdef CONFIG_PHY_MICREL_KSZ90X1 phy_micrel_ksz90x1_init(); #endif +#ifdef CONFIG_PHY_MESON_GXL + phy_meson_gxl_init(); +#endif #ifdef CONFIG_PHY_NATSEMI phy_natsemi_init(); #endif diff --git a/include/phy.h b/include/phy.h index a0b1f12..50f1e12 100644 --- a/include/phy.h +++ b/include/phy.h @@ -268,6 +268,7 @@ int phy_lxt_init(void); int phy_marvell_init(void); int phy_micrel_ksz8xxx_init(void); int phy_micrel_ksz90x1_init(void); +int phy_meson_gxl_init(void); int phy_natsemi_init(void); int phy_realtek_init(void); int phy_smsc_init(void);