From patchwork Thu Oct 5 13:07:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "See, Chin Liang" X-Patchwork-Id: 821769 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3y7CvL0TJ0z9s82 for ; Fri, 6 Oct 2017 00:15:58 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B91B5C21C62; Thu, 5 Oct 2017 13:12:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5455AC21F96; Thu, 5 Oct 2017 13:08:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 585B9C21FD4; Thu, 5 Oct 2017 13:08:03 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id 99311C21FB8 for ; Thu, 5 Oct 2017 13:07:58 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Oct 2017 06:07:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,481,1500966000"; d="scan'208";a="907051212" Received: from pg-interactive1.altera.com ([137.57.137.156]) by FMSMGA003.fm.intel.com with ESMTP; 05 Oct 2017 06:07:55 -0700 From: chin.liang.see@intel.com To: u-boot@lists.denx.de, Marek Vasut Date: Thu, 5 Oct 2017 21:07:28 +0800 Message-Id: <1507208851-32672-12-git-send-email-chin.liang.see@intel.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1507208851-32672-1-git-send-email-chin.liang.see@intel.com> References: <1507208851-32672-1-git-send-email-chin.liang.see@intel.com> Cc: Tien Fong Chee , Chin Liang See Subject: [U-Boot] [PATCH v2 11/14] arm: socfpga: stratix10: Add timer support for Stratix10 SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Chin Liang See Add timer support for Stratix SoC Signed-off-by: Chin Liang See Reviewed-by: Dinh Nguyen --- arch/arm/mach-socfpga/timer.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index 253cde3..23450b0 100644 --- a/arch/arm/mach-socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2016-2017 Intel Corporation + * Copyright (C) 2012-2016 Altera Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,15 +11,29 @@ #define TIMER_LOAD_VAL 0xFFFFFFFF +#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10) static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; +#endif /* * Timer initialization */ int timer_init(void) { +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) + int enable = 0x3; /* timer enable + output signal masked */ + int loadval = ~0; + + /* enable system counter */ + writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS); + /* enable processor pysical counter */ + asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); + asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); + +#else writel(TIMER_LOAD_VAL, &timer_base->load_val); writel(TIMER_LOAD_VAL, &timer_base->curr_val); writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl); +#endif return 0; }