From patchwork Tue Sep 19 18:38:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 815785 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QP54/3Xj"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxWzy4GnCz9s7m for ; Wed, 20 Sep 2017 04:46:22 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 23BEEC21C50; Tue, 19 Sep 2017 18:44:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D7D20C21D6A; Tue, 19 Sep 2017 18:44:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4E7BDC21DA1; Tue, 19 Sep 2017 18:43:49 +0000 (UTC) Received: from mail-pg0-f66.google.com (mail-pg0-f66.google.com [74.125.83.66]) by lists.denx.de (Postfix) with ESMTPS id EEA7BC21DA1 for ; Tue, 19 Sep 2017 18:43:44 +0000 (UTC) Received: by mail-pg0-f66.google.com with SMTP id m30so256157pgn.5 for ; Tue, 19 Sep 2017 11:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ng/ixNpJanBi4dJcYZWzPUmJc7Fy+AkUsbW/ZYRn9KE=; b=QP54/3XjnZfUhLijgZ4giabDM79opsS/E4vGItKMA1tv6vKbRVbaT2CiUxHma0aylB d26vHBJ2hKg+aCgXXF9GRAXi4XxgV316MwvA257RQO6Ciqc1ks6JA8JYYdSA4KLHGVBy 2tXBHhTTEAFccjbSaGW2XnUOmRBH6ugbsE8oXsVawUqphH2zdfKDaPT9aTpucjNx1EN/ dmgnmelXEYfm0k4O9B38g2VJy14wzbU7hT8wQcUN5aZSHrLEW4WS14s9QGdPk84ImAoK mPhFSPnnJOxAcNTD3vnMgIy3xfLRNRp9juAxMM6cNZFXa0OLJgYmZIXFMuQal/s6hTFv HFmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ng/ixNpJanBi4dJcYZWzPUmJc7Fy+AkUsbW/ZYRn9KE=; b=rhcE/Yqree8Lq4aI0gx37rMUzgXB5+AfbWaYANV7GaQVtOJw+3qCYzufr7CITzFZTA 3tMRvh65YHc01EJdSvqIy6iV055PqDwEYho2Dc7SbPsj3q4uHPh4KQKdv5XeiGXZRZdt Z0BKp6r/CVdNfjntbFD7oflD4pqJtp591dfr9IHi5w1+EMFjOIUFFCp8iUvhWOpoZzV3 UOGhpdEB9KRrNbSishouDmYzcgdffyJ2wuW7CNGjjzERH/9erecj+alztKR0/zzslJtX 35Aww3KA9FqCHzl3wszYFrdOVfTsJu43zWruAOyefhJ0XoHrtY9KoMZBtIL3ilD9Ez2a C93A== X-Gm-Message-State: AHPjjUhZ4Vhq8REdYr1RArL+Oc2euv32mfjV3m+QLCR10uNQM1r0rrNY MImYg9J3zCe3jbyOv1Iiu7U= X-Google-Smtp-Source: AOwi7QBVoJ0mWBH9u5Wp4o9rhtrNZdD7Ccs2ZKao1dAQb8LIBCD6USAHJOjI2wZerIIRceu28xi81A== X-Received: by 10.99.95.147 with SMTP id t141mr2271499pgb.340.1505846623501; Tue, 19 Sep 2017 11:43:43 -0700 (PDT) Received: from localhost.localdomain ([115.97.191.18]) by smtp.gmail.com with ESMTPSA id e87sm4757779pfl.46.2017.09.19.11.43.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 11:43:41 -0700 (PDT) From: Jagan Teki X-Google-Original-From: Jagan Teki To: Stefano Babic Date: Wed, 20 Sep 2017 00:08:00 +0530 Message-Id: <1505846281-19020-6-git-send-email-jteki@openedev.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505846281-19020-1-git-send-email-jteki@openedev.com> References: <1505846281-19020-1-git-send-email-jteki@openedev.com> Cc: Fabio Estevam , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 5/6] i.MX6Q: icore: Add SPL_OF_CONTROL support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Add OF_CONTROL support for SPL code. Signed-off-by: Jagan Teki --- arch/arm/dts/imx6qdl-icore-rqs.dtsi | 2 + arch/arm/dts/imx6qdl-icore.dtsi | 2 + arch/arm/dts/imx6qdl.dtsi | 5 ++ arch/arm/mach-imx/mx6/Kconfig | 8 +++ board/engicam/icorem6/icorem6.c | 75 ----------------------- board/engicam/icorem6_rqs/icorem6_rqs.c | 102 -------------------------------- configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_rqs_defconfig | 1 + include/configs/imx6-engicam.h | 22 +++---- 9 files changed, 31 insertions(+), 187 deletions(-) diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi index 8b9d5b4..65cbf5a 100644 --- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi @@ -100,6 +100,7 @@ }; &usdhc3 { + u-boot,dm-spl; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; @@ -165,6 +166,7 @@ }; pinctrl_usdhc3: usdhc3grp { + u-boot,dm-spl; fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi index a485c3e..06d9bc3 100644 --- a/arch/arm/dts/imx6qdl-icore.dtsi +++ b/arch/arm/dts/imx6qdl-icore.dtsi @@ -118,6 +118,7 @@ }; &usdhc1 { + u-boot,dm-spl; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; @@ -208,6 +209,7 @@ }; pinctrl_usdhc1: usdhc1grp { + u-boot,dm-spl; fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070 diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index b13b0b2..e04b570 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -77,6 +77,7 @@ compatible = "simple-bus"; interrupt-parent = <&gpc>; ranges; + u-boot,dm-spl; dma_apbh: dma-apbh@00110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; @@ -225,6 +226,7 @@ #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; + u-boot,dm-spl; spba-bus@02000000 { compatible = "fsl,spba-bus", "simple-bus"; @@ -516,6 +518,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + u-boot,dm-spl; }; gpio2: gpio@020a0000 { @@ -805,6 +808,7 @@ iomuxc: iomuxc@020e0000 { compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; reg = <0x020e0000 0x4000>; + u-boot,dm-spl; }; ldb: ldb@020e0008 { @@ -889,6 +893,7 @@ #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; + u-boot,dm-spl; crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 540f2b2..9f2b30c 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -198,6 +198,10 @@ config TARGET_MX6Q_ICORE select DM_THERMAL select SUPPORT_SPL select SPL_LOAD_FIT + select SPL_DM if SPL + select SPL_OF_CONTROL if SPL + select SPL_SEPARATE_BSS if SPL + select SPL_PINCTRL if SPL config TARGET_MX6Q_ICORE_RQS bool "Support Engicam i.Core RQS" @@ -213,6 +217,10 @@ config TARGET_MX6Q_ICORE_RQS select DM_THERMAL select SUPPORT_SPL select SPL_LOAD_FIT + select SPL_DM if SPL + select SPL_OF_CONTROL if SPL + select SPL_SEPARATE_BSS if SPL + select SPL_PINCTRL if SPL config TARGET_MX6SABREAUTO bool "mx6sabreauto" diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index e173124..a967ccd 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -7,7 +7,6 @@ */ #include -#include #include #include @@ -191,77 +190,3 @@ void setup_display(void) writel(reg, &iomux->gpr[3]); } #endif /* CONFIG_VIDEO_IPUV3 */ - -#ifdef CONFIG_SPL_BUILD -/* MMC board initialization is needed till adding DM support in SPL */ -#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) -#include -#include - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ -}; - -#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) - -struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC1_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 USDHC1 - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - SETUP_IOMUX_PADS(usdhc1_pads); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - default: - printf("Warning - USDHC%d controller not supporting\n", - i + 1); - return 0; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning: failed to initialize mmc dev %d\n", i); - return ret; - } - } - - return 0; -} -#endif -#endif /* CONFIG_SPL_BUILD */ diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c index 599cea3..c0a6d4f 100644 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -6,21 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include -#include - -#include -#include -#include - -#include -#include -#include -#include #include -#include - -#include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -35,93 +21,6 @@ int board_mmc_get_env_dev(int devno) #ifdef CONFIG_SPL_BUILD #include -/* MMC board initialization is needed till adding DM support in SPL */ -#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) -#include -#include - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR, 1, 4}, - {USDHC4_BASE_ADDR, 1, 8}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC3_BASE_ADDR: - case USDHC4_BASE_ADDR: - ret = 1; - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - - /* - * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) - * mmc0 USDHC3 - * mmc1 USDHC4 - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 1: - SETUP_IOMUX_PADS(usdhc4_pads); - usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning - USDHC%d controller not supporting\n", - i + 1); - return 0; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning: failed to initialize mmc dev %d\n", i); - return ret; - } - } - - return 0; -} - #ifdef CONFIG_ENV_IS_IN_MMC void board_boot_order(u32 *spl_boot_list) { @@ -147,5 +46,4 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[0] = boot_dev; } #endif -#endif #endif /* CONFIG_SPL_BUILD */ diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 1b001df..221866a 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -49,3 +49,4 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_VIDEO_IPUV3=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index a57a992..e6b4dff 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -41,3 +41,4 @@ CONFIG_FEC_MXC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_MXC_UART=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index c34dc30..ddbd6dd 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -219,16 +219,18 @@ # include "imx6_spl.h" # ifdef CONFIG_SPL_BUILD -# if defined(CONFIG_TARGET_MX6Q_ICORE_RQS) || defined(CONFIG_TARGET_MX6UL_ISIOT) -# define CONFIG_SYS_FSL_USDHC_NUM 2 -# else -# define CONFIG_SYS_FSL_USDHC_NUM 1 -# endif - -# define CONFIG_SYS_FSL_ESDHC_ADDR 0 -# undef CONFIG_DM_GPIO -# undef CONFIG_DM_MMC -# endif +# if defined(CONFIG_IMX6UL) +# if defined(CONFIG_TARGET_MX6UL_ISIOT) +# define CONFIG_SYS_FSL_USDHC_NUM 2 +# else +# define CONFIG_SYS_FSL_USDHC_NUM 1 +# endif + +# define CONFIG_SYS_FSL_ESDHC_ADDR 0 +# undef CONFIG_DM_GPIO +# undef CONFIG_DM_MMC +# endif /* CONFIG_IMX6UL */ +# endif /* CONFIG_SPL_BUILD */ #endif #endif /* __IMX6_ENGICAM_CONFIG_H */