Message ID | 1503573163-22389-1-git-send-email-priyanka.jain@nxp.com |
---|---|
State | Accepted |
Commit | 033c538e567aca5f0876f2504b5e278c2a0f83a8 |
Delegated to: | York Sun |
Headers | show
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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR03MB2263 Cc: Priyanka Jain <priyanka.jain@nxp.com> Subject: [U-Boot] [PATCH][v2]drivers:net:fsl-mc: Update MC address calculation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <http://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> |
On 08/24/2017 04:14 AM, Priyanka Jain wrote: > Update MC address calculation as per MC design requirement > of address as least significant 512MB address > of MC private allocated memory, i.e. address should point > to end address masked with 512MB offset in private DRAM block. > > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> > Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> > --- > Changes for v2: Updated description and code comment > to clarify more on MC design requirement based on York suggestion. > Revised commit message. Applied to fsl-qoriq master. Thanks. York
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 3a30c03..284737c 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -800,12 +800,19 @@ int get_dpl_apply_status(void) return mc_dpl_applied; } -/** +/* * Return the MC address of private DRAM block. + * As per MC design document, MC initial base address + * should be least significant 512MB address of MC private + * memory, i.e. address should point to end address masked + * with 512MB offset in private DRAM block. */ u64 mc_get_dram_addr(void) { - return gd->arch.resv_ram; + size_t mc_ram_size = mc_get_dram_block_size(); + + return (gd->arch.resv_ram + mc_ram_size - 1) & + MC_RAM_BASE_ADDR_ALIGNMENT_MASK; } /**